RGPV Previous Question Papers BE 4th Semester Computer System and Organization June 2009

RGPV Previous Question Papers BE 4th Semester

Computer System and Organization June 2009

(Comman for CS/EC&IT, Engg.)

Note:     The question paper is divided into five units. Each units carries an internal choice. Attempt one

question from each unit . Thus  attempted five questions in all. All question carries equally

marks. Assume suitable data whenever necessary. A should be laconic.

1.   (a)    What is an instruction? What are the different parts of an instruction?

A machine support 16-bit instruction format the size of address expanding epode technique and

Has 55000 zero address instruction. Find out the number of two- address instruction sported by

This machine.

(b)    What is addressing mode? An instruction is stored at location is stored at location 300 with its

has vides at3001. The address files have the value 400. A processor register R1 contains the

Number 200.Evaluat the effective address if the addressing mode of the instruction is :

(i) Direct                             (ii) Immediate

(ii) Register indirect          (iv) Relative

(v) Index with R1 as the index register

2.           Describe the mechanism of an instruction fetching decoding and execution using flowchart.

(b)    What are the different addressing modes supported by 8085 microprocessor? Explain each with


©    Draw non-Neumann architecture. What is meant by Von-Neumann Bottleneck?

3.  (a)    With the help of a neat diagram and example . Explain the working of a typical microprogramed

control unit.

(b)   Show the step-by-step multiplication process using Both algorithm , When the following binary

number are multiplied . Assume 5-bit register that hold signed number –

(i) (+15) × (+13)     (ii)  (+15) × (+13)


4.    (a)  With the block diagram , explain the working principle of microprograme sequencer.

(b)  Design an array multiplier that multiplies two 4-bit numbers . Use AND binary address .

5.   (a)  What are the function performed by an I/O interface? Explain with an example.

(b)    Draw the block diagram of asynchronous communication interface and also explain the

Operation transmitter and receiver [portion of the interface.

©    Compare I/O versus memory bus.

6.  (a)   Explain the responsibilities of a typical DMA  controller. A DMA controller transfer 16 bit words to

memory using cycle sealing . the words are assembled from a device that transmit character at

a rate of 2400 character/sec, the CPU fetching the executive instruction/sec, By how much will

be CPU be slaw down because of a DMA transfer?

(b)      Explain the interrupt structure of 8085 microprocessor.

7.  (a)  What is paging? Explain how paging can be implemented in CPU to access virtual memory.

(b)   Explain what is meant by a cache memory. What general principle are used to make effective

uses of cache memory?

A two-ways set associate each memory uses block of our four words. The cache can

Accommodate a total of 2048 words from main memory. The main memory size is 128 K * 32.

(i)    How many bits are there in the tag .index, block and word field of address format?

(ii)    What is the size of cache memory ?

8.  (a)  Draw the typical memory model. How can be categorize the memory on the basis os Access time

. Configuration and technology used?

(b)  A virtual memory system has an address space of 8k words, A memory space of 4K words and

page and block size o 1K words . The following page references change soccer during a given time

Interval –


Determine the four pages that are resident in main memory after each page reference changes

if the replacement algorithm used as:

(i) LRU     (ii) LFU   (iii) FIFO

9.    (a)   Why does pipelining improve performance? What are the various instruction hazards which

affect the performance of pipeline processor? Also explain their impact and throughput.

(b)    Explain and draw the model of crossbar switch organization for establishing an

Interconnection network in multiprocessor system . How many switch point are there in a

crossbar switch network the connects p processors to m memory modulates ?

10.  (a)     A non pipelined system take 100 ns to process a task . The same task can be processed in a six-

segment pipeline with a clock cycle of 20 ns . Determine the speedup ratio of the pipeline for

200 tasks. What is the maximum speedup that can be achieved?

(b)    What is the purpose of system bus controller? Explain the how the system can be designed

to distinguish between to reference to local memory and reference to conman shared


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