RGPV Previous Question Papers BE 4th Sem Computer System and Organization Dec 2011

RGPV Previous Question Papers BE 4th Semester

Computer System and Organization Dec 2011

(Comman for CS,EC&IT, Engg.)


Note: Attempt one questions from each unit.

Total question to be attempted are five. All question carry equal marks.

1.   (a)  Discuss the organization of 8085 microprocessor . What are the different flag s of 8085 flag


(b)       Explain the following

(i)  Micro operation

(ii)  Macro operation

(iii)  Program counters

(iv)  Instruction cycle

(iv) Input output instruction

2.  (a)  Draw a conman bus system with four register with the help of multiplexers.

(b)  A digital computer has common bus system for 16 register of 32 bits each. The bus is constructed

with multiplexer.

(i)  How many selection input are in each multiplexer?

(ii) What size of multiplexer in need?

(iii) How many multiplexer are there in the bus?

3.  (a)  Explain  how the mapping from an instruction code to a microinstruction address can be done by

means of a read only memory.

(b)  With the help of block diagram , describe the organization of a microprogramming  unit.

4.  (a)  Explain the following in detail.

(i) Address sequencing

(ii) Hardwired control unit.

(b)      Draw and explain the organization of a CPU showing the connections between the register to a

comman bus.

5.  (a)  Differentiate between the following –

(i) Synchronous and asynchronous modes of serial data transfer

(ii) interrupt initialized I/O  and direct memory access.

(b)    Explain in brief the instruction set of 8085 microprocessor (Give only types of instruction )

6.   (a)  What are the different types of DMA techniques ? Explain the basic principle of DMA.

(b)  Explain priority interrupt and polling in context to interrupt initialed I/O

7.  (a)    What is meant by memory hierarchy in a computer system also explain what is meant by

associative memory and virtual memory?

(b)    Explain the following relation to  cache memory-

(i) Locality of reference

(ii) Hit ratio

(iii) Mapping

(iv) Writing into cache

(v) cache initialization

8.  (a)    Explain memory protection and memory segmentation by memory management hardware .

(b)    The access time of a cache memory is 100 ns and that of main memory is 1000 ns .It is

estimated that 80 % of the memory requests are for read and 20% for write. The hit ratio for

read access is 0.9 . A write though procedure is used –

(i)   What is the average access time of the system considering only memory read cycle ?

(ii) What is the average access time of the system for both read and write requests

(iii) What is the hit ratio taking into taking into consideration write cycle ?

9.          What is pipelining ? What is the need of pipelining? Explain the pipeline organization of an

arithmetic pipelines .

10.        Write short notes on any two of the following:

(i) Vector processor and array processor.

(ii) Interconnection structure

(iii) Interprocess communication

(iv) Memory interleaving.

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