RGPV Previous Question Papers BE 4th Sem Computer System and Organization Dec 2004

RGPV Previous Question Papers BE 4th Semester

Computer System and Organization Dec 2004

(Comman for CS,EC & IT Engg.)

Note: Attempt any five questions.

All question carry equal marks.

1. (a)      Write the fetch and execute cycle for the following instruction

(i)       AND     (ii)     LDA        (iii)     BSA

(b)      Draw the block diagram for  the hardware that implements the following statement –

(i)   x+yz:AR←AR+BR      (ii)    x+xy+xz:AR← AR+1 where AR and BR are two n-bit registers and x,y

and z are control variables.

2.   (a)    Explain the difference between hardwired control and microprgrammed control .  Is it possible

to have a hardwired control associated with a control memory? Write in short.

(b)    What is the purpose of micro program sequencer? Explain its internal structure and working in

detail.

3.   (a)   How the addition and subtraction is done for fixed point number ? Explain it by drawing

flowchart.

(b)   Divide (-12) by (+3) using division algorithm.

4.   (a)    What do you mean by serial transmission and parallel transmission of data ? Compare them .

(b)     What do you mean by handshaking? How data is transferred by source initiated data transfer

using hand – shaking? Explain it by timing diagram and sequence of events diagram.

5.            What is cache memory? How is it organized by direct mapping? Explain.

6.   (a)     Perform the arithmetic operation  ( Ai *Bi) + (Ci*Di) with a stream of number . Specify a pipeline

Configuration to carry out this task. list the contents of all register in the pipeline for i

=1through 6.

(b)   Formulate a six-segment instruction pipeline for a computer. Specify the operation to be

performed in each segment.

7.    (a)   Explain in short how BCD addition is carried out in 4 bit BCD adder.

(b)   What is the function of IOP (input/output processor) ? Explain it with block diagram.

8.            Write short notes on any three of the following –

(i)    Interrupt Initiated data transfer

(ii)   Addressing modes

(iii)  Daisy – chaining priority

(iv)  Associative memory

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