Digital Electronics January 2013

UNIT – I

1 (a) Prove the following :

(i) A®B-A®B

(ii) A®B=A®B=A®B (hi) B®{B®AC) = AC

(b) Convert the following numbers from given base to the other base indicated

 (i) (102.25)10 = ( ? >2 (ii) (101.001)2 = ( ? )io (in) II

COh(iv)(2F9A)16 = (? >8(v)(247.36)8 = (? )l6

OR

1 (a) Convert the given code to other code :

(i) (32 7.89) l0 = (BCD) code

(ii) (4096) 10 = (Excess – 3) code

(iii) (0100 0111)BCD = ( ? ) gray code

(b) Explain the following with one example :

(i) Hamming distance

(ii) Alphanumeric code.

(c.) Perform the following Addition/Substraction :

(i) (54)- (2A)lfi

(ii) (123)8 + (001)8 + (203)8

UNIT – II

2 (a) Draw the circuit diagram of 3-input NAND gate using TTL logic and find the expression for fan out.

(b) Draw circuit for 2-input NOR using CMOS and explain its working. Also compare the advantage and disadvantages of CMOS’ logic with other.

OR

2. (a) Define the following and give one example for each :

(i)  Propagation delay

(ii) Wired logic

(iii) Schottky diode clamping

(iv) RTL logic.

(b) What is difference between Saturation logic and Active logic. Explain these with one example and show their speed capability.

UNIT – III

3 (a) Minimise the four variable logic function using K-map :

(i)f{A, B, C, D) = Ym 235> 7>89>1114)

(ii)f (A, B, C, D) = n m (4, 6,10,12,13,15)

(b) Simplify the following logic expression using K-map and implement them using NAND gate :

(i)y = (a+b+c)(a+b + c)(b+c+d)

(ii)Y = ABCD + ARC!) + ABC + ABD + B.

OR

3 (a) Minimise the following expression with don’t care conditions using K-map :

(i) 7 = 5>(l,3,7,15)+tf(0,2,5)

(h) F = n /»(4, 5, 6, 7,8,12) + </ (0,1,2,9,11,14).

(b) Explain the Quinn-Mcklusky minimization technique with one example.

UNIT – IV

4. (a) Design a Gray-to binary code converter logic circuit.

(b) Implement the following logic expression using multiplexer :

(i)  jf^I>0>2A5,6)

(ii) Y = n m (0,1, 2, 5, 7).

OR

(a) Design a BCD to Excess-3 encoder.

(b) Realise the following :

(i) Y – ^ m (0,1, 2,3,11,12,14,15) using 16 : 1 multiplexer.

(ii) Y = Unt (0,1,3, 7, 9,10,11,13,14,15) using 4 to 16 line decoder.

UNIT – V

5. (a) Convert the following :

(i)  J-K FF to S – R FF

(ii) D FF to J-K FF.

(b) Draw the logic circuit for Asynchronous modulo-10 counter and draw its waveform :

OR

(a) Draw the state diagram of :

(i)  JK FF

(ii) 4 bit binary counter.

(b) Design a sequence detector to detect a serial input sequence 1010. Draw its state diagram, state table, state assignment table and final implemented circuit.