Pune University Exam Paper VLSI Design and Technology

B.E. (E & TC) VLSI DESIGN AND TECHNOLOGY (2008 Pattern) (Sem. – I)

Time :3 Hours]                                                                           [Max. Marks :100

Instructions to the candidates:

1)           Answer any three questions from each section.

2)           Answers to the two sections should be written in separate books.

3)           Neat diagrams must be drawn wherever necessary.

4)           Figures to the right indicate full marks.

5)           Use of logarithmic tables, slide rule, Mollier charts, electronic pocket calculator and steam tables is allowed.

6)           Assume suitable data, if necessary.

SECTION – I

QI) a) With I-V characteristics explain MOSFET as current source and current sink.       [12]

b) Write note on source follower.                                                                            [4]

OR

Q2) a) Draw and explain Standard cascode and High swing cascode.                        [10]

b) Draw and explain CMOS differential amplifier using NMOS                      [6]

Q3) a) Draw voltage transfer characteristics of CMOS inverter and explain different regions of operation of NMOS and PMOS transistor. [10]

b) What is the dynamic power dissipation? Explain the significance of power delay product.                                                                                                                       [6]

OR

Q4) a) What is Technology scaling? Explain different design rule check in terms of X parameters.                                                                                                           [10]

b) Write short note on body effect.                                                                          [6]

 

Q5) a) What is Test Bench? Describe Synthesizable and Non-Synthesizable test bench.  [8]

b) What is Function and Procedure? Describe it with VHDL example. [10]

OR

Q6) a) Draw state diagram and write VHDL code for Traffic Light Controller.

[14]

b) Write a short note on Metastability.                                                                  [4]

SECTION – II

Q7) Draw and explain the detail Architecture of CPLD.                          [16]

OR

Q8) Differentiate between CPLD and FPGA; also write 4 specification of each. Device. [16]

Q9) a) What is the need of DFT? Explain different types of faults.                           [12]

b) What is Controllability and Predictability?                                                      [6]

OR

Q1O) Write short note on BIST, JTAG and TAP controller.                                       [18]

QII) a) What is clock skew and clock jitter? Explain different techniques of clock distribution.                                                                                                          [10]

b) Write short note on wire parasitics.                                                                   [6]

OR

Q12) a) Write note on Power Distribution and Power Optimization.                         [10]

b) Explain different EMI design consideration.                                                                                        [6]

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