Pune University BE Question Paper VLSI Design

B.E. (Electrical) VLSI DESIGN (2008 Pattern) (Elective – III) (Sem. – II)

Time: 3 Hours]                                                                                              [Max. Marks :100

Instructions to the candidates:

1)            Answer 3 questions from Section -1 and 3 questions from Section – II.

2)            Answers to the two sections should be written in separate books.

3)            Neat diagrams must be drawn wherever necessary.

4)            Figures to the right indicate full marks.

5)             Use of logarithmic tables slide rule, Mollier charts, electronic pocket calculator and steam tables is allowed.

6)            Assume suitable data, if necessary.

SECTION – I

Q1) a) Draw state diagram to detect 1011 sequence using mealy and moore model.         [8]

b) Draw the timing diagram of MOD 6 Asynchronous counter and MOD 6 Synchronous counter.                                                                                                   [10]

OR

Q2) a) Implement AND, OR, NAND, NOR gate using 4 : 1 multiplexer. [8] b) Draw state transition table for MOD 11 counter using T flip-flop. Also implement its Design diagram. [10]

Q3) a) Explain EDA tool Design flow.                                                           [8]

b) Define the terms :                                                                                                    [8]

i)   Entity         ii) Architecture

iii) Component           iv) Configuration

OR

Q4) a) State and explain any 4 types of data types & data objects used in VHDL.   [8]

b) Write VHDL code for 8 : 1 multiplexer & also draw its internal circuit diagram.            [8]

Q5) a)

What do you mean by sub-program overloading? Explain with example

 

using VHDL code.

[8]

b)

Write VHDL code for R-S flip-flop using process statement.

[8]

  OR  

Q6) a)

Which are the nine different values of std-logic? Also write entity to

 

create an array of 8 x 8 with data type as std-logic vector.

[8]

b)

What do you mean by configuration? Explain with an example in

 

VHDL code.

[8]

  SECTION – II  

Q7) a)

Explain voltage transfer characteristics of CMOS invertor.

[8]

b)

Explain the construction of MOSFET device.

[8]

  OR  

Q8) a)

Define the concept of FAN-IN, FAN-OUT figure of merit and Noise

 

margin w.r.t. CMOS. Also state its standard values.

[8]

b)

State standard device specifications of MOSFET.

[8]

Q9) a)

Draw and explain Architecture of FPGA.

[8]

b)

Write a note on simulation and Synthesis.

[8]

  OR  

Q10)a)

Differentiate PAL and PLA.

[8]

b)

Draw and explain standard Architecture of CPLD.

[8]

Q11)a)

Write VHDL code for 4 bit Adder.

[8]

b)

Write VHDL code for 8 x 8 RAM.

[10]

  OR  

Q12)a)

Draw block diagram of ALU & also write its VHDL code.

[8]

b)

Write VHDL code for 4 bit shift register with parallel load and serial

 

right shift output.

[10]

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