Pune University BE Electronics VLSI Design Question Papers

Pune University BE Electronics VLSI Design Question Papers

B.E. (Electronics) VLSI DESIGN (2008 Pattern) (Sem. -1)

Time :3 Hours]                                                                           [Max. Marks :100

Instructions to the candidates:

1)            Answer any 3 questions from each section.

2)            Answers to the two sections should be written in separate answer books.

3)             Neat diagrams must be drawn wherever necessary.

4)             Pigures to the right indicate full marks.

5)             Use of logarithmic tables, slide rule, Mollier charts, electronic pocket calculator and steam tables is allowed.

6)            Assume suitable data, if necessary.

SECTION – I

QIA a) Draw CMOS Inverter and explain Voltage Transfer Curve in detail. [8] b) Derive the expressions for Static and Dynamic power dissipations. Compare them.                  [8]

OR

Q2) a) Design 4:1 multiplexer using Transmission Gate and compare it with conventional method.                                                                                        [8]

b) What is feature size and X ? List basic X rules in CMOS design. What is DRC, SRC & ERC?                                                                                                          [8]

Q3) a) Explain read / write operation of 6T SRAM cell with the help of timing diagrams.                                                                                                              [8]

b) Differentiate between SRAM 8 DRAM technologies.                                    [8]

OR

Q4) a) Draw the schematic of DRAM cell with necessary peripherals and explain read / write cycles with the help of timing diagrams.                                             [8]

b) Give the classification of memory with the applications of each. [8]

Q5) a) Write VHDL code for 4 bit resettable UP/DOWN counter. Also write test bench for it.                                                                                                                     [W]

b) With suitable examples explain delta delay, inertial delay and transport delay.   [W]

OR

Q6) a) Write a VHDL code for 4 bit shift register, using structural modeling. Also write test bench for it.                                                                            [W]

b) What are different modeling styles of architecture? How to make a decision to use a particular style?                                                                                       [W]

SECTION – II

Q7) a)

Draw the block diagram of CPLD and List its specifications.

[8]

b)

Differentiate between FPGA 8 CPLD.

[8]

OR

Q8) a)

Draw the block diagram and explain in detail the architecture of FPGA. [8]

b)

Explain how half adder logic gets implemented in FPGA and CPLD

differently. Explain with suitable schematic.

[8]

Q9) a)

Explain with block diagrams, Full 8 Partial Scan path arrangements. [8]

b)

Explain in detail stuck at fault model.

[8]

OR

Q10) a)

What is the need of design for testability? With schematic explain different

Faults.

[8]

b)

Explain TAP controller with state diagram.

[8]

Q11)a)

Explain Global and Switch box routing.

[W]

b)

Explain off chip connection and I/O architecture.

[W]

 

OR

Q12)Write short notes on the following:                                                                        [18]

a)            Power distribution and optimization.

b)           Two phase clocking and clock distribution.

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