Pune University BE CSE VLSI and Digital System Design
B.E. (Computer Engineering) VLSI & DIGITAL SYSTEM DESIGN (2008 Pattern)
(Elective – IV) (Sem. – II)
Time :3 Hours] [Max. Marks :100
Instructions to the candidates:
1) Answer three questions from Section I and three questions from Section II.
2) Answers to the two sections should be written in separate answer books.
3) Neat diagrams must be drawn wherever necessary.
4) Pigures to the right indicate full marks.
5) Assume suitable data, if necessary.
SECTION – I
QI) a) Explain VLSI Design Flow. 
b) Draw and explain physical structure of an nMOS enhancement transistor.
Q2) a) Draw and explain structure and model of an NPN bipolar transistor alongwith its VI characteristics. 
b) Explain briefly about semiconductor technology families. 
Q3) a) Explain in detail a basic n-well CMOS process alongwith suitable diagram.
b) What is Shallow Trench Isolation? Explain STI process flow. 
Q4) a) Explain in detail steps involved in silicon on insulator (SOI) CMOS process along with neat diagram. 
b) Explain photolithography process in detail.
Q5) a) Explain basic concept of crystal structure. Also explain unitcell and miller indices.
b) What is principle of thermal oxidation. Explain: Regenerative thermal and catalytic oxidizer.
Explain in detail: 
i) Wet Etching.
ii) Plasma Etching.
What is chemical vapor deposition and physical vapor deposition explain its types. 
SECTION – II
Explain architecture of FPGA. What is selection criterion of FPGA in application? 
Explain operator overloading in VHDL. 
Write code in VHDL for 4:1 multiplexer in three different modeling types.
Write a note on shift operators. 
Define following terms with respect to CMOS circuits: 
i) Fan Out.
ii) Transition Time.
iii) Propagation delay and
iv) Power consumption.
Discuss logic levels and noise margins with respect to CMOS circuits. 
Discuss the advantages of digital circuits over analog circuits.  Write short note on :
i) Hamming code and
ii) CRC code.
Listout different design steps for clocked synchronous state machine. 
Draw a neat diagram and explain briefly internal structure of synchronous SRAM. 
Explain in brief applications of parity checking. 
Explain along with suitable logic diagram PAL16L8.