Pune University Advanced Computer Architecture Previous Exam
B.E. (Electronics) ADVANCED COMPUTER ARCHITECTURE (2008 Pattern) (Sem. – I)
(Elective – II)
Time :3 Hours] [Max. Marks :100
Instructions to the candidates:-
1) Answer any 3 questions from each section.
2) Answers to the two sections should be written in separate books.
3) Neat diagrams must be drawn wherever necessary.
4) Assume suitable data, if necessary.
SECTION – I
QI) a) Explain the Amdahl’s law for speedup performance. 
b) Why do we need high speed computing? Explain the Von-neuman computer architecture and its limitations. 
c) Write a short note on: Instruction level Parallelism. 
Q2) a) Explain in brief Fengs classification and Handlers classification for Parallel computer architectures. 
b) State the various applications of Parallel processing. Explain the application of Parallel processing in weather forecasting. 
Q3) a) Explain the architecture of Itanium Processor in detail. 
b) Define the following terms: 
i) Forbidden Latency.
ii) Collision Vector.
iii) Simple Cycle.
iv) Greedy Cycle.
v) MAL – (Minimum average latency)
Q4) a) State the key features of SPARC. Explain in brief Register window structure of SPARC. 
b) What do you mean by EPIC? State and explain features of EPIC. 
Q5) a) How does Vectorization work? Explain any two vector optimizing functions. 
b) Explain : Vector loops and pipeline chaining. 
Q6) a) State the characteristics of CRAY – I computer system. Draw and explain the computation section of CRAY – I vector processor. 
b) State the desirable features of parallel languages. 
SECTION – II
Q7) a) Explain matrix Multiplication on SIMD architecture. 
b) Explain the algorithm to compute fast fourier transform for SIMD architecture. 
Q8) Explain the various interconnection networks used for interconnecting the processors in parallel computer system along with their salient features. 
Q9) a) Give a typical architecture for MPP. Explain in detail. 
b) Explain the cache coherency problem explain the “Write-invalid” protocol.
QIO) a) What is chip Multiprocessing. With block diagram explain the architecture of IBM power 4 processor. 
b) Write a note on : Inter process Communication and Synchronization. 
Qll)a) Discuss in brief Latency hiding Techniques with respect to multithreaded architecture. 
b) Explain use of following primitives w.r.t. parallel programming. 
i) Send ( );
ii) Receive ( );
iii) Fork ( );
iv) Join ( );
Ql2)a) State the following terms w.r.t. multithreading. 
ii) Context switching overhead.
iii) Interleaved multithreading
iv) Latency hiding
b) What is data parallel programming. Explain in detail.