WBUT Question Papers EE Digital Electronics And Integrated Circuits B Tech 4th Sem June 2008

WBUT Question Papers EE

Digital Electronics And Integrated Circuits B Tech 4th Sem June 2008

 

Time : 3 Hours )

Full Marks : 70

GROUP-A ( Multiple Choice Type Questions )

  1. Choose the correct alternatives for any ten of the following :       10×1 = 10
  2. i)                The minimum number of NAND gates required to implement ( A + AB’ + AB’ C’ )

a) zero                   b) on

c) four                   d) seven.

ii)              Conversion of ( 36-532 )8 into equivalent hexadecimal number is a) ( 1F-AE )16  * b) ( IE-AD )16

c) ( 1F -AD )16            d) None of these.

iii)            Conversion of ( 564 )10 Into Gray code is

a)     1100101110    b) 1110100110

c) 0111001011             d) 1000110100.

iv)            If tp is the pulse width, At is the propagation delay arid T is the period of pulse

train, then which one of the following conditions can avoid the race around conditions ?

a)   tp = At = T            b) 2tp > At > T

c) tp < At < T            d) 2tp < At < T.

v)  The equation V213 = 13 is valid for which one of the number systems with base ?

a)  Base 8                       b) Base 6                          ’

c) Base 5                 d) Base 4.


CS/a.TECH (EE-HSW)/UM-4/CC (BB) 403/M

vi) Which one of the following is a self complementing code ?

 

 

 

a) Ex-3 code c) 8421 code

b) Gray code d) None of these.

 

 

 

b) 10 kHz

d) None of these.

a) 60 ns c) 20 ns

b) 40 ns

d)

none of these.

ix) If the negative logic is used, the diode gate shown in the given figure will represent         .

o = ov

V = -5V

 

vii) A clock frequency of 100 kHz is applied to MOD – 8 followed by a decade counter. What will be the output frequency ?

 

viii) A 3-bit synchronous counter uses flip-flops with propagation delay time of 20 ns each. The maximum possible time required for change of state will be

 

a) OR gate c) NOR gate

b) AND gate d) NAND gate.

 

 

 

x) The minimum number of NAND gates required to implement A+AB+ABC is equal to

 

 

a) 0

c) 4

b)

d)

1

7.

 

 

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xi) In standard TTL, the “totem pole” stage refers to the

a)   multi-emitteer i/p stage    b) phase splitter

c) o/p buffer             d) open collector o/p stage. | 1

xli) The SOP form of logical expression is most suitable for designing logic circuits using only

a)     XOR gates b) NOR gates

c) NANDgaes               d) OR gates.             I I

GROUP -B

Answer any three of the following.     3×5= 15

  1. What is fen out ? What is the basic difference of a latch and edge triggered flip-flop ? Design a 9-bit even parity generator circuit. 1 + 1+ 3
  2. Design BCD-Excess 3 code converter using basic logic gates with proper truth table. 5
  3. What is Race Around condition ? Explain the working of Master-Slave Flip-flop. 1+4
  4. Draw a neat diagram of a R-2R ladder type DAC and explain its operation.                                                  5
  5. Draw the neat diagram of a 4 bit Bi-directiohal Shift register using mode control ( M ). When M is logic zero then left shift and right shift for M are logic one.
  6. Answer any three of the following questions.
  7. GROUP -C (Long Answer Type Questions )
  1. a) What do you mean t>y Prime implicant ? Simplify the following Boolean

expression using K>map:

F ( A, B, C, D ) = 2 m ( 0, 2, 3, 6, 8, 11, 12, 14 ) + d ( 1,4,9, 10 } ,

b)               Design full adder using two half adders and necessary gate.

c)               Draw a network using only NAND gate to generate the function Y -(A+BC).

  1. a) What afe the advantage and disadvantage of totem pole ?(

b)              What are the output voltages caused by logic 1 in each bit position in an 8 bit ladder If the input level for 0 level is 0 volt and for level 1 is 10 volt ?

c)               Compare the maximum conversion period of an 8 bit Digital ramp ADC and 8 bit successive approximation ADC if both utilize 1 MHz clock frequency ?

d)              With proper circuit diagram explain the operation of NMOS NAND gate. 3 + 3 + 4 + 5

  1. a) Perform the conversion-of D -flip-flop to-J-K flip-flop.

b)              What is presettable counter ? Design a MOD-5 counter that counts its natural count sequence from 000 to 100.

c)  Distinguish between a ripple counter and synchronous Counter.  5 + 8 + 2

  1. a) What are the differences between the Decoder and Demultiplexer ?

b)               Form a multiplexer tree to give 4X1 MUX from two 2X1 MUX:

c)               Show how a 16 input MUX is used to generate the function

F >. (A,B»C,D) – ABCD+BCD + ABC+ABCD.

  1. a) What are RAM and ROM ? What is the basic difference between EPROM and EEROM ?

b)   What is the major difference between the two classes of finite state machines and proper state diagram ?

c)What is Schmitt Trigger ?

IV-247322 {3ft)

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