WBUT Question Papers CS Advanced Computer Architecture B Tech Forth Sem June – 2008

WBUT Question Papers CS

Advanced Computer Architecture  B Tech Forth Sem June – 2008

GROUP-A (Multiple Choice Type Questions)

  1. Choose the correct alternatives for the following :                         10 x 1 = 10

4 The seek time of a disk is 30 ms. It rotates at the rate of 30 rotations/second. The capacity of each track is 300 words. The access time is approximate^

a)       62 ms    b) 60 ms

c)       47 ms    d) none of these.

Ji) The performance of a pipelined processor suffers if.

a)              the pipeline stages have different delays

b)               consecutive instructions are dependent on each other

c)               the pipeline stages share hardware resources .

d)              all of these.

Consider the high speed 40 ns memory cache with a successful hit ratio of 80%. The regular memory has an access time of 100 ns. What is the effective access time for CPU to access memory ?


52 ns 70 ns



60 ns 80 ns.





What is a main advantage of classical vector systems (VS ) compared with RISC based systems ( RS) ?

VS have significantly higher memory bandwidth than RS

VS have higher clock rate than RS

VS are more parallel than RS None of these.

v) Associative memoiy iaa                                ^

a)              pointer addressable memoiy

b)              very cheap memoiy                  .

c)                     content addressable memoiy – d) slow memoxy.

vi)             The principle of locality justifies the use of

£0 Interrupts             b) Polling

c) DMA                    d) Cache memoiy.

vii)           How many address bits are required for a 512 x 4 memoiy ?

a)               512                       b) 4           * ‘

c) 9                      d) A0 – A6.                |

viii)         A single bus structure is primarily found In

a)              Main frames

b)              High performance machines

c)              Mini and Micro- computers

d)              Supercomputers. ■

ixj What will be the speed up for a four-stage linear pipeline, when the number of instruction rt = 64 ?

a)                                                                                                                            4.5  b) 7.1

c) 6.5                    d) None of these.

x} Dynamic pipdine allows

a)              multiples function to evaluate

b)              only streamline connection

c)               to perform fixed function

d)            none of these.                                    : IV-2448SS (S-A)


GROUP-B ( Short Answer Type Questions)

  • Answer any three of the following.                                      3 x 5 = IE
  1. What are the different parameters used in measuring CPU performance ? Briefly discuss each.    5
  2. What do you mean by m-way memory interleaving ? In the system with pipeline processing, is the memoiy interleaving useful ? If yes, explain why.                                                                     2 + 3
  3. Develop 32 x 42 delta network.                                                                                           5
  4. Compare superscalar, super-pipeline and VLIW techniques.                                          5
  5. Discuss about strip mining and vector stride in vector processors.                           3 + 2

GROUP -C (Long Answer Type Questions)

Answer any three of the following.    3 x 15 = 45

  1. a) What is Multistage Switching Network ?
  2. b) Describe the distribution and shared memoiy model of SIMD architecture.
  3. c) Draw the block diagram and explain the functionality of processing element.

2 + 8 + 5

  1. a) What is meant by pipeline stall ?

b)               Draw the block diagram of C-access memoiy function. Why is it necessaiy and how does it improve the memoiy access time ?

c)  Implement the data routing logic of SIMD architecture to compute


s ( k) = X Ai for fc = 0, 1, 2…N-1.

i = o

d)               A computer has cache access time of 100 nanosecs, a main memoiy access time of 1000 nanosecs and a hit ratio of 0.9.

0 Find the average access time of the memoiy system

ii) Suppose that in the computer, there is no cache memoiy, then find the

  • average access time, when the main memory access time is 1000 nanosecs. Compare the two access times.    2 + 4 + 4 + E
  1. zO What is Memory Management Unit (MMU) ?

b)               What are the advantages of using cache memory organization ? Define hit ratio. Compare and contrast associative mapping and direct mappin

Draw a 16-input Omega network using 2 x 2 Switches as building blocks :

i) Show the switching setting for routing a message from node 1011 to node 0101 and from node 0111 to node 1001 simultaneously. Does blocking ‘ exist in this case ?

11) Determine how many permutations can be implemented in one-pass through this Omega network. What is the percentage of one-pass permutations among all permutations 7

. HI) What is the maximum number of passes needed to implement any permutation through the network ?         2 + 7 + 6

  1. a) What do you mean by “Data flow Computer” ?

b)              With simple diagram, explain Data flow architecture and compare it with control flow architecture.

c)               Draw data flow graphs to represent the following computations :

0 X = A + B
U) Y = X/B
iii) Z = A*X,
iv) M = Z-Y
v) N IIN


vi) P = M/N.


d)               What is vector processor ? Give the block diagram to indicate he architecture of a typical Vector Processor with multiple function pipes.                                         2 + 6 + 3 + 4

  1. Write short notes on any three of the following :                          3×5

a)               Omega Network                ‘

b)               Cross bar Switches

c)               Reservation table

d)               Multiport Network

e)               CM-2 machine.

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