WBUT Previous Years Question Papers CS Computer Organization B Tech 3rd Sem Dec 2006
WBUT Previous Years Question Papers CS
Computer Organization B Tech 3rd Sem Dec 2006
Time : 3 Hours ]
[ Full Marks : 70 Group – A (Multiple Choice Questions)
- Choose the correct answers for the following : 10 x 1 = 10
i) Subtractor can be Implemented using
a] adder b)
c) both (a) & (b) d)
10 Overflow occurs when
a) data is out of range
b) data is within range
c) none of these.
ill) Instruction cycle is
a) fetch-decode-execution b) c) fetch-execution-decode d)
iv) Cache memory a) Increases performance b) c) machine cycle increases d)
v) In microprogramming
a) horizontal microinstruction is faster
b) vertical microinstruction is faster
c) hardware control unit is faster
d) none of these.
vi) Associative memory is a
a) very cheap memory
b) pointer addressable memory
c) content addressable memory
d) slow memory.
vli) The speed of a microprocessor is usually measured by the
a) microprocessor’s throughput
b) speed with which it performs I/P and O/P operations
c) time required to execute a basic instruction
d) time required to process a small operation.
viii) For BIOS ( Basic Input / Output System ) and IOCS ( Input / Output Control System ), which one of the following is true ?
a) BIOS and IOCS are same
b) BIOS controls all devices and IOCS controls only certain devices
c) BIOS is not a part of Operating System and IOCS is a part of Operating System
d) BIOS is stored in ROM and IOCS is stored in RAM.
ix) How many RAM chips of size ( 256 K x 1 bit) are required to build 1 M Byte memory ?
a) 8 b) 10
c) 24 d) 32. |
x) Whidh logic gate has the highest speed ?
a) DTL b) RTL
c) ECL d) TTL. [
Group – B ( Short Answer Questions )Write short notes on any three. 3 x 5 = 15
- Stack memory
- Pipeline processor
- Virtual memory
- IEEE format for floating point representation.
( Long Answer Questions )
Answer any three questions.
What are the bottlenecks of the von Neumann concept ? Discuss the role of the operating system.
Show the bus connection with a CPU to connect four RAM chips of size 256 x 8 bits each and a ROM chip of 512 x 8 bit size. Assume the CPU has 8-bit data bus and 16-bit address bus. Clearly specify generation of chip select signals. 5
Briefly explain the two write policies write through and write back for cache design. What are the advantages and disadvantages of both the methods ? 5
What is interrupt ? What are the differences between vectored and nonvectored interrupt ? 1+4
i) Why is refreshing required in Dynamic MOS ? 2
ii) Define volatile and non-volatile memory. 3
How do ALU and CU work ? Explain. 3 + 2
What is Bus ? How many buses are present in computer ? ‘ 1+2
What is “Dumb” memory ? 1
What is dirty bit ? 1
Draw a block diagram to illustrate the basic organisation of computer system and explain the function of various units. 8
What is input device ? How does it differ from output device ? 2
Draw the logic diagram and discuss the advantages of a carry look ahead adder over conventional parallel adder. 5
Discuss with suitable logic diagram the operation of an SRAM cell. 5
What are the different status flags in a processor ? Discuss overflow detection. 5
- a) Explain Booth’s Algorithm with flow-chart and suitable example. 8
- b) Compare Restoring with Non-restoring division algorithms. 2
- c) Explain sequential circuit and combinational circuit and give two examples. 5
- a) What are the different types of DMA controllers and how do they differ in their
- functioning ? 7
- b) How does work polling ? 3
- c) What is instruction cycle ? Draw time diagram for memory read operation. 1+4