VTU Previous Question Papers BE EC 8th Semester
Embedded System Design June 08
Note : Answer any FIVE full questions.
1 a. Differentiate between the following
i) Single purpose and general purpose processors.
ii) Full custom IC and PLD technologies
b. Explain the following terms
i) Characteristics of an embedded system
ii) Ideal top – down design process.
c. Define time – to – market and NRE cost metrics. The lifetime of a product is 64 weeks. If the product is delayed by 7 weeks, determine the percentage revenue loss. Determine the per – product cost, if the NRE cost is Rs 4,00,000 and unit cost is Rs 8000 and the company produces 5000 units of that product.
2 a. Write s simple algorithm for finding the GCD of two integer numbers. Write the FSMD for this algorithm and explain how it can be optimized and write the optimized FSMD and its advantages.
b. Explain the following 3 addressing modes with an example from any processor.
i) Register indirect
ii) Relative addressing
iii) Direct 4
3 a. Explain the following terms
i) Superscalar architecture
iii) Dhrystone Benchmark
iv) Cross compiler
b. Differentiate between
i) Harvard and Princeton architectures
ii) Microcontrollers and DSPs.
c. Explain pipelining. If 6000 instructions are to be executed using a 4 stage pipelined processor at a clock frequency of 12 MHz. determine the speedup of the pipelined processor when compared to a non – pipelined processor.
4 a. Describe the working of PWM with necessary diagrams and explain how it can be used in the speed control of DC motor.
b. What is a WDT and what is its use? A 16 bit timer operates at a clock frequency of 20 MHz. Determine the resolution and range of this timer. If a 4 – prescaler is also used, what is the range and resolution of this design? (06 Marks)
c. The analog input range for an 8 bit ADC is from -2.5 V to + 7.5 V. Determine the resolution of ADC and digital output in hexadecimal when the input voltage is 1.2 V. Trace successive approximation steps and show the binary output of the ADC.
5 a. Compare the following
i) SRAM and DRAM
ii) Direct mapped and fully associative cache memory designs.
b. Explain the following terms in brief
i) Flash memory
c. Compose lk x 8 ROMs for the design of a 2 k x 16ROM. Write a block diagram showi the connections and the memory map. Determine the average memory access time, if i cache miss ratio is 0.2, cache access requires 2 cycles and main memory access requires cycles when the clock frequency is 20 MHz.
6 a. Explain shared data problem with an example show how interrupt facility can be used solving this problem.
b. Compare i) CAN Bus and PCI Bus ii) Serial and Parallel communication.
c. Consider three processes with high, medium and low priorities respectively. The executi time values of these three processes be lOOjn sec, 200p, sec and 300p sec respectively. T minimum interrupts latency of the system be 150jj, sec. Let the deadline of the low prior process be 600jx sec. Is it possible for the low priority process to execute before 1 deadline if the other two interrupts also occur or only medium priority process interruj it? Determine the worst case Interrupt latency values for both the cases.
7 a. Describe RR with interrupts with an algorithm. Mention a practical application for 1 same.
b. Explain RTOS architecture with an algorithm.
c. Compare the characteristics of the four software architectures for scheduling. (06 Marl
8 a. Write a major difference for the following topics
i) Queues and Mailboxes
ii) Ready and Running states
iii) Encapsulating semaphores and encapsulating queues
iv) Saving memory space and saving power.
b. What are semaphores? Explain the structure and use of binary semaphores for da protection.
c. Explain the 2 rules that the interrupt routines in a RTOS must follow.