VTU Previous Question Papers BE CS 4th Semester Computer Organization July 2006

VTU CSE 4th Semester Computer Organization July 2006

VTU CSE 4th Semester Computer Organization Question Paper July 2006: To score better marks in the 4th semester, you should have depth knowledge in every subject. You can boost your preparation by solving previous year question papers. I will give you information about the important chapters and concepts to be covered in all chapters.

Here we are providing you the complete guide on VTU CSE 4th Semester Computer Organization Question Paper July 2006.

VTU CSE 4th Semester Computer Organization Question Paper July 2006

You must have Computer Organization Question Paper along with the latest Computer Science 4th sem Syllabus to enhance your semester exam preparation.

Here you can check the VTU CSE 4th Semester Computer Organization Question Paper July 2006

1. Answer any FIVE full questions.

2. Answer should be brief and to the point

1. a. Distinguish between :

i) Pipelining and super scalar operation

ii) CISC and RISC

 iii)Multiprocessors and multicomputers.

(b)Explain clearly SPEC Rating and its significance.

(c)Convert the following pairs of numbers to 5 bit signed 2’s complement binary numbers and add them. State whether an overflow occurs in each case.

i)-14 and 11 ii) -10 and -13.

(d)Discuss the two ways in which byte addresses are assigned across words.

2. a. Explain with a specific example how a stack frame is built and dismantled for a particular invocation of a subroutine.

 (b) Which of the following possibilities for saving return address of a subroutine support subroutine nesting and which support subroutine recursion and why?

 i)  in a processor register

 ii) in a memory location associated with call on a stack.

(c) Explain clearly the Bus Arbitration Methods.

3. a. Draw a combined input / output interface circuit and explain the different operations clearly.

 (b) Consider a synchronous bus that transfers data in one clock cycle. Address transmitted by the processor appears on the bus after 4 nanoseconds, propagation delay on the bus varies from 1 to 5 nanoseconds, address decoding takes 6 nanoseconds. Addressed device takes 5 to 10 nanoseconds to place the data on the bus. Input buffer needs 3 nanoseconds setup time. Estimate the clock speed at which this bus can operate.

(c)Distinguish between the processor clock speed and bus clock speed and explain why the disparity occurs between the two. State the values of the above in a modern computing system.

4. a) Discuss the main phases involved in the operation of SCSI bus in detail.

b) Explain the operation of a split bus with a diagram.

c)  With a diagram explain USB packet format clearly.

5. a) Draw a block diagram for 8m X 32 memory system using 512 k X 8 memory chips and explain its operation. Discuss direct napped, associative mapped and set associative mapped CACHE memory system with suitable diagrams.

b)Define Hit Rate and Miss Penalty.

6. a. Show the organization of a typical associative mapped TLB and explain how address truncation takes place.

(b) Explain the organization and how data is accessed from a disk. State the typical values for recording surfaces, tracks, sectors, bytes / sectors, access time in a disk.

7 a. Discuss the Booth’s Multiplication Algorithm with an example.

(b) With a clear diagram explain the floating point addition -subtraction unit.

8.(a) With a diagram which shows the separation Decoding and Encoding functions. Explain hard wired control

(b) With a block diagram explain an embedded processor with all the salient blocks and their functions.

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