VTU Previous Exam Papers BE EC 6th Semester Analog and Mixed Mode VLSI Design Dec.09-Jan.10

VTU Previous Exam  Papers BE EC 6th Semester

 Analog and Mixed Mode VLSI Design Dec.09-Jan.10

 

Note: 1. Answer any FIVE full questions, selecting at least TWO questions from each part.

2.Standard notations are used.

3.Missing data be suitably assumed.

PART-A

1 Define Resolution, INL, DNL and Vfs for a DAC.

(b)Find the maximum DNL and INL in LSBs of a characteristic. Check if it is monotonic. bit DAC which has the following

Digital input     000     001     010      011    100     101    110     111

Analog output  0V  0.625 V   1.5625 V   2.0 V  2.5 V  3.125 V   3.4375 V  4.375V

 

(c)Find the maximum resolution of an ADC which can use the S/H circuit with maximum sampling error of 0.628 mV while maintaining a sampling error less than 1/2 Vref = 5 V

 

2 (a) Discuss the issues involved in mixed signal circuit layout.

(b)Describe the simple resistor string DAC, problem associated with it and how is it overcome by use of a binary switch array.

 

3 (a)Describe the pipelined ADC with a neat diagram.

(b)For an 8 bit pipelined ADC, all the amplifiers had a gain of 2.1 v/v instead of 2v v. Vin = 3 V and Vref = 5 V, what would be the resulting digital output, assuming ot er components are ideal.

(c)For a 4 bit successive approximation ADC with Vref = 5V, Vjn = IV, find the output digita^ code. Assume a dual slope successive approximation ADC. For each clock cycle, give output of the S AR, Vaut and the final output.

 

4 (a)Discuss the advantages and disadvantages of using a dual slope over a single Slope ADC

(b)Draw the CMOS analog multiplier and explain its working.

(c)Discuss transient response, propagation delay and minimum slewrate of a comparator.

PART-B

5 (a)Develop an expression for effective number of bits in terms of the measured SNR  If the input wave has a peak amplitude of 30% of VRef.

(b) With a neat block diagram, describe the accumlate and dump circuit for decimation averaging.

(c)Sketch the block level circuit diagram for an fs/4 digital resonator.

 

6 (a)With relevant diagrams, describe the CMOS process flow, for devices with Lmin<0.35µm.

(b)Describe with a neat diagram, the conceptual layout and actual layout of an R~2R resistor string with minimum area and also discuss the problem of laying out metal over the resistive material.

7 (a)Sketch the implementation of a synchronous up/down counter and discuss its operation.

(b)Draw the 4 bit pipelined adder and describe how it operates.

(c)Draw the positive edge triggered delay using clocked CMOS logic.

8 (a)Illustrate how a pushpull output stage is biased with a floating current source.

(b)Infer that, to minimize the input referred noise, the gain of the first stage of the amp i should be large in a cascade of amplifiers.

(c) Discuss circuit noise m an opamp.

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