Mumbai University question papers
III Sem CSE- Examination June 2009
Computer Organisation and Architecture
N.B.: (1) Question No.1 is compulsory.
(2). Solve any four questions out of remaining.
(3) Draw neat labeled diagram wherever necessary.
1. (a) Explain with suitable examples the difference between computer architecture and computer organization.
(b) Define the following terms:
(i) Memory Access Time (MAT)
(ii) Memory Cycle Time (MCT)
(iii) Spatial locality of reference
(iv) Temporallocality of reference
(v) Cache block.
(c) Explain IEEE format for floating point number representation.
2. (a) Explain and solve the following problem using by restoring division algorithm? Hence divide (163)10 with (11)10′
(b) A 32- bit computer has a 32 bit memory address. It has 8 KB of cache memory. The computer follows four-way set associative mapping. Eacb line sizeis 16bytes.Showthememoryaddressformatand cache~emory organization.
3. (a). Whatis memoryinterleaving? Discuss variousmemory interleavingtechniques.
(b) Explain the general organization of CPU? State the fun~tion of following CPU registers.
(i) MAR (Memory Address Register)
(ii) MDR (Memory Data Register)
(iii) IR (Instruction Register)
(iv) PC (Program Counter)
(v) SP (Stack Pointer).
4. (a) What is Virtualmemory? Explain how paging is useful in implementingvirtual memory?
(b) Define “(Input/Output) I/O Module?” State the difference between programmable and non-programmable device? Explain in brief DMA data transfer techniques with diagram.
Con. 2874-VR-3324-09. 2
5. (a) Define the term “softwired” and “hard wired” Explain nano-programming.
(b) What is “Micro program”? Write a Micro program using RTL(register transfer language) notation for the following arithmetic operation.
(i) SUB RI,R2 i.e RI~ RI – R2
(ii) MUL RI,R2 i.e RI ~ RI*R2
6. (a) Explain in brief about SPARC processor? Draw and explain in brief n-bit windows architecture of SPARC processor?
(b) Explain the Flynn’s Classification in detail?
7. (a) What is pipelining? Show that Kstage pipe lined processor has K times speed up compared to a non pipe lined systems.
(b) Explain wave front array with suitable example?