Mumbai University Previous year question papers
V Sem Electronics Examination May 2010
Microprocessor and Microcontroller-2
N.B. : (1) Question No. one is compulsory.
(2) Attempt any four from remaining six questions.
Q.1a) In an Design a 8086 based system with following specifications CPU at 10MHz in minimum mode operation 32 KB SRAM using 8 KB devices 64 KB EPROM using 16 KB devices Design system with exhaustive decoding. Clearly show memory map with address ranges and draw a neat schematic for chip selection logic.
b) Explain :n brief support devices in P!C18F microcontroller and their’use. 08
Q.2a) Write a program for performing a 64 bit I 16 bit division using 8086 instruction set. The operands and the result is to be stored in memory. 1.0
b) Explain following 8086 instructions 10
a) STD b) MOVS c) AAS d) IMUL e) RCL
Q.3a) Write a program to generate a rectangular wave on 8255 port A with ON time = 2* OFF time. Explain the mode in which 8255 is used and its mode set control word.
Q.3b) What are different function blocks in 8259 Programmable Interrupt Controller? Explain the role of IRR, ISR, IMR, and priority resolver in process of interrupt handling.
Q.4a) Explain different modes of operation of 8237 DMA Controller. 10
b) Write a program to calculate delay of 100 microsecond using PIC18F microcontroller (freq = 40 MHz)
Q.5a) Explain block diagram of PIC18F architecture in brief with a neat diagram. 12
b) In the following program, find the contents of Register 03h and identify the 08
flags set at the end.
Explain the program
Q.6a) Write a program to divide the unsigned a 16 bit number OFOFH stored in data registers REG 1 and REG2 (MSB in REG2) by 8. ,
Q.6b) Interface two common cathode seven segment LEOs to PIC18F microcontroller using PORT B and PORT C. Explain the working with the help of neat diagram and suitable program.
Q.7a) Explain working and interface of numeric Data coprocessor 8087 with 8086 10
b) What are exceptions, hardware interrupts and software ;nterrupts ,of 8086. 10
Explain their priority structure and interrupt vector table.