Mumbai University Previous year question papers Digital System Design I June 2008

Mumbai University Previous year question papers

III Sem Electronics Examination June 2008

Digital System Design-I

 

1. (a) Draw a circuit diagram of a CMOS inverter. Draw its transfer characteristic and explain its operation.

(b) \ Find static hazards in the circuit given below and modify the circuit to eliminate the hazard. 10

 

2.(a) (i) Convert to Hexadecimal number (367.32)10

(ii) Solve using 2’s complement method. (48)10 – (32)10

(iii) Convert (351.02)5 to base 7 number.

(iv) Divide (10101)2 by (10)2

(v) Convert (AOBO)4 to Binary.

(b) Implement the following function using only one 4:1 mux and minimum number of gates. 10

F(A BCD) = Lm (2, 3, 4, 5, 9, 11) + L d( 0, 1)

 

3. (a) Explain the essential features of VHDL and write a VHDL program for active low 3:8 deqoder. 10

(b) Define the following parameters of logic families and give values for CMOS logic family. 10

(i) Fan out

(H) figure of merit

(iii) Propagation delay time

(iv) Noise margin

(v) Current parameters.

 

4.(a) Write a VHDL code for an 8 to – 3 priority encoder using conditional signal assignment. 10

 (b) Implement the following functions using active low decoder :- 10

(i) F (A, B, C) =Lm (1,2,4,5)

F(A, B, C) = nM(1, 3, 5, 7) [ Do not convert to SOP-form]

 

5. (a) Convert (1) SR FF to T FF and

 (2) D FF to JK. FF .

 (b) Implement the two functions using (i) PLA and

 F1(ABCD)=Lm(5,8,9, 12, 13)

F2 (A BCD) =Lm (1, 3, 5, 8, 9, 11)

(ii.) PAL 10

 

6. (a) Implement BCD adder using 4 bit binary adder IC 7483. Explain its operation by adding 0101 and 0110.

(b) Using K map, simplify the following expressions and implement them using only NOR gates 10

 (i) F(A BCD) =Lm ( 0, 1, 3, 4, 6, 9, 11, 12, 14)

(ii) F(A BCD) =Lm (4, 6,12,14) + Ld (1, 3, 9,11)

 

7. (a) Explain working of comparator IC 7485 and implement 10 bit comparator using same ICS.

 (b) Write short notes on any two :-

 (i) Parity generator and checker IC 74180

 (ii) Quine McCluskey method

 (iii) Interfacing TTL and CMOS logic families.

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