# Mumbai University Previous year question papers

Table of Contents

## III Sem Electronics Examination Dec 2008

## Digital System Design-I

N.B.: (1) Question no. 1 is compulsory.

(2) Solve any four from remaining six questions.

1. Answer th~ following questions :-

(a) Generate a 7 bit even parity hamming code for” 1010″.

(b) Simplify the following expression using Boolean theorems (AB+C+D) (C+D) (C+D+E)

(c) Explain lockout condition with the help of 3 bit Ring counter.

(d) Draw a Karnaugh Mapfor the given circuit

2.

(a) Implement the following function using NAND gates oI1ly–

F= Lm(l, 2, 4,7, 11, 13) + d (9, 15)

(b) Design a combinational Circuit for controlling panel light of satellite control 12

room. The Light should go ON if :-

The pressure in fuel and oxidizer tank is equal to or above the required minimum and there are 10 minutes or less for the satellite to lift off.

Or

The pressure in fuel tank is below the required minimum but there are more than 10 minutes for the satellite to lift off.

Or

The pressure in oxidizer tank is below the required minimum but there are more than 10 minutes for the satellite to lift off.

3..(a) Design a 4: 1MUXwith active high enable input using NORga~es only.

(b) Using Quine McCluskey Simplification Method simplify

F=Lm(I,3, 13, 15)+Ld(8,9, to, 11)

4. (a) Design a 4-bit even parity generator and checker. Implement using one 10

8:1 MUXeach.

(b) Design a 1 digit BCD adder using IC 7483 and explain the operation for 10

(0101)BCD+ (l001) ~CD

5. (a) What are reflective codes? qive suitable example and explain.

(b) Define following parameters for CMOS logic family and give values :-

(i) Fan out

(ii) Propagation Delay

(iii) Noise Margin

(iv) Current Parameters.

(c) Find’the static hazard in the given circuit and modify it to eliminate the hazard-

6. (a) Design a synchronous 4 bit universal * upl *down counter.

(b) De~ign a MOD 6 asynchronous counter and explain glitch problem.

7. (a) Generate “101” sequence by using shift register in S1S0 mode. Draw timing diagram.

(b) Design XYFlip-Flop using JKFlip-Flop:-