Mumbai University Previous year question papers Digital Logic Design and Application Dec 2007

Mumbai University Previous year question papers

 III Sem CSE – Examination Dec 2007

Digital Logic Design and Application

N.B.(1) Question No.1 is compulsory.

(2) Attempt any four questions out of the remaining six questions.

(3) Assume suitable additional data if required.

1. (a) Fill in the blanks :-

(i) A number in any number system can be represented by the following equation

(ii) The excess 3 code is

(iii) While adding two BCD numbers, if the sum gives an invalid BCD code, then to make it valid

(iv) Two’s complement of a numer is

(v) Eight bits make a and four bits make a

(b) Consider the MN FF as shown. Obtain its characteristic table, characteristic equation and excitation table. .

(c) Carry out following arithmatic without converting to any other base.

(i) (B 6 A)16 (ii) (7 5 6 )9-( 2 F E)1c6 X ( 5 3 )9

(d) A seven bit Hamming Code is received as 1000010. Correct it for any errors. Why Hamming Code is called as error correcting code? Justify. .

(e) Subtract (365)8 from (173)8′ Use 8’s complement addition to perform subtraction.

2. (a) Simplify using Boolean Theorems and implement using AOI gates only.

(i) [( C+ CD) (C + CD)] [( AB+ AB) + (A EiJB) ]

(ii) AB + AB + (A+B).(A+B)

(b) Given the logical expression-

Y = (A + B + C + D). (A+C+D).(B+C)( B+C).(A+B)(B+D)

(i) Express in std pas fprm

(ii) Draw K map for the equation.

(iii) Minimize and realise using NOR gates only.

3. (a) Realise FULLSubtractor circuit using 4 : 1 Multiplexer and 3L : 8L Decoder. [ Active high lip and Active low alp decoder]

(b) Using Quine McCluskey Method, determine the minimal SOP form for:

F(A, B, C, D, E, F, G) = l:m ( 20, 28, 38, 39, 52, 60, 102, 103, 127)

4. (a) The Computer Engineering Society wishes to select members on its board of Governers. The following criterias ar~ applied. The candidate should be a member of the society for a minimum period of 12 years. A male candidate s~ould have a professional experience of 20 years or more. A female candidate will be eligible if she has an experience of 15 years. Design and implement the above circuit.

(b) Design and implement two “2.bit multiplier circuit.

5. (a) For synchronous sequence counter with sequence 2 6 5 3 – 1- 0 – 2

(i) Give present statelnext

state table

(ii) Write state transition table using D flip-flops.

(iii) Simplify and realize the circu’it. Draw state diagram.

(iv) If th~ counter enters any unused state will it go to lockout condition. Justify.

(b) Draw neat diagram of two lip TTL NAND gate and explain its operation.

6. (a) What is Shift Register? Explain 4 bit bi-directional shift register. 10

(b) Design mod 13 asynchronous down counter. What is glitch problem? How to avoid glitch ?

7. (a) What is Multiplexer? Implement F =1t

M( 0, 1, 4, 5, 7, 11, 14) using 16 : 1 multiplexer.

(b) Write short notes on [any two]

(i) Master slave JK flip-flop

(ii) 74180 parity generator and checker

(iii) PAL and PLA. .

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