# Mumbai University Previous year question papers

Table of Contents

## III Sem CSE – Examination DEC 2009

## Digital Logic Design and Application

N.B.:(1) Question No.1 is compulsory.

(2) Attempt any four questions out of remaining six questions.

1. (a) Convert (2009.12)10 into octal and hexadecimal.

(b) Design (1:16) demultiplexer using (1:4).

(c) Design a full subtractor using a decode.r and additional gates.

(d) Simplify and implement using gates:

y = AB ( B + C) + AB (B + C)

(e) State and prove DeMorgan’s theorem.

2. (a) Simplify using K-map, obtain POS equation and realize using NOR gates: 10

f(A, B, C, D) =1t M (1, 3, 4, 5, 9, 10, 11).d(6,8).

(b) Draw a twisted ring cpi.mter and prove that it is “Divide by 2 N” circuit, where ‘N’ is number of Flip ‘Flops. Show necessar-y timing diagrams.

3. (a) Prove NAND as universal gate. 10

(b) Compare TTl, CMOS and ECl families with respect to basic gate, voltage levels,fan-in, fan-out,/propagationdelay/power dissipationand noise margin.

4. (a) Simplify using Quine McClusky method and real’ize using any universal Gate:

F(P, Q, R, S) = Lm(1, 2, 6, 8, 10, 11, 14, 15) + d(5, 9).

(b) Implement the following expression using 8:1 MUX. 10

f(A, B, C, D) = Lm(O, 1/ 3, 5, 7, 10, 11, 13, 14, 15).

5. (a) Design a 3-bit even gnd odd parity generator. 10

(b) Design a maximum length sequence generator, to generate the sequence 1101001 and repeat.

6. (a) Design a 2-bit digital comparator that accepts inputs A and Band gives three outputs G, E and L.

(i) Output G is ac’iive, when A > B.

(ii) Output E is active, when A = B.

(iii) Output L is active, when A < B.

(b) Draw a 4-bit universal shift register and explain.

7. Write short notes on the following :-

(a) Totem pole output stage of TTl gate.

(b) Priority encoder.:’

(c) Current and voltage parameters of logic gates.

(d) Race around condition in J-K Flip-Flop.