Mumbai University Previous year question papers Digital Logic Design and Application Dec 2008

Mumbai University Previous year question papers

 III Sem CSE – Examination Dec 2008

Digital Logic Design and Application

N.S.: (1) Question No.1 is c.ompulsory.

(2) Attempt any four questions out of remaining six questions.

(3) Assume suitable data and state it clearly’. .

1. (a) Convert (157.63)8 into decimal, binary and hexadecimal system.

(b) Simplify using boolean laws:

AB + A + AB

(c) Design full adder using half adders.

(d) State and prove De Morgan’s theorem.

(e) Implement the boolean function with NANDNAND logic

F(A, B, C) =L m(O, 1, 3, 5)

2. (a) Using boolean laws, prove NAND and NOR gates as universal gates.

(b) Draw 3-bit binary up-down counter and explain the operation.

3. (a) What is race condition? How it is overcome in Master-slave J-K flip flop? Explain. 10

(b) State truth table of 3 bit gray to binary conversion and design using 3 : 8 decoder and additional gates.

4. (a) Simplifyusing K-map,f(A, B, C, D) =1t

M( 0, 2, 3, 6, 7, 8, 9, 12, 13)Write simplified SOP and P~S equations and draw logical diagram using NAND gates only.

(b) Simplify the function using Quine McClusky method. f(A, B, C, D) =L m(4, 5, B, 10 9, 11, 12, 13, 15) Draw the logical diagram using NAND gates.

5. (a) Draw a 2-input TTL NAND gate and explain its operation.

(b) Simplify F(P, Q, R, S) =1t

M(3, 4, 5, 6, 7, 1O, 11, 15) and implement using minimum no. of gates.

6. (a) Design MOD-6 synchronous counter and explain its operation.

(b) Draw 4 bit universal shift register and explain its operation.

7. Write short notes on :-

(a) Multiplexer and demultiplexer

(b) ALU

(c) Asynchronous vs synchronous counter

(d) Octal to binary encoder.

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