JNTU Supplimentary Examinations, February 2008
Vlsi Systems Design
1. Implement the following gates with p-MOS transistors only and explain its working
(a) 3 -Input NAND gate.
2. (a) Why CMOS technology is most suitable for VLSI ICs?
(b) Compare between CMOS and bipolar technologies.
3. Design a stick diagram for two-input P-MOS NAND and NOR gates.
4. Implement 2-input NOR and NAND gates using static complementary logic.
5. Explain the procedure to optimize power consumption of an isolated logic gate.
6. Draw the circuit diagram of four transistor DRAM cell with storage nodes and explain its working.
7. Explain how power – down modes reduces the power consumption of the design.
8. Explain about design methodology for 1BM ASICS.