JNTU question papers – B -Tech II Semester Examinations, VLSI Design, Apr/May 2008
JNTU B.Tech II Semester Examinations, VLSI DESIGN, Apr/May 2008
( Common to Electronics & Communication Engineering, Bio-Medical
Engineering and Electronics & Telematics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
1. With neat sketches, explain in detail, all the steps involved in electron lithography
2. (a) Explain nMOS inverter and latch up in CMOS circuits?
(b) Draw the nMOS transistor circuit model and explain various components of the model. [8+8]
3. Draw the stick diagram and mask layout for a CMOS two input NOR gate and stick diagram of two input NAND gate. 
4. (a) Explain the concept of sheet resistance and apply it to compute the ON resistance (VDD to GND) of an NMOS inverter having pull up to pull down ratio of 4:1, If n channel resistance is Rsn = 104 per square.
(b) Calculate the gate capacitance value of 5?m technology minimum size transistor with gate to channel capacitance value is 4 × 10?4pF/?m2. [10+6]
5. (a) Explain the CMOS system design based on the data path operators with a
(b) Draw and explain the basic Memory- chip architecture. [8+8]
6. (a) What are the characteristics of 22V10 PAL CMOS device and draw its I/O structure.
(b) Explain any one chip architecture that used the antifuse and give its advantages. [8+8]
7. (a) What are the different types of operators used in VHDL? Give some examples
(b) Compare the Circuit-level, Logic-level, switch-level and Timing simulations. [8+8]
8. (a) compare functionality test and manufacturing test.
(b) What type of testing techniques are suitable for the following:
ii. Random logic
iii. Data path.
(c) How IDDQ testing is used to test the bridge faults? [5+6+5]