JNTU IV B.Tech I Semester Supplimentary Examinations, February 2008

JNTU IV B.Tech I Semester Supplimentary Examinations, February 2008

VLSI SYSTEMS DESIGN

SET-I

1. Implement the following gates with CMOS Logic and explain its working

(a) Ex-OR gate.

(b) 2 – Input NOR gate. [8+8]

2. (a) Define the terms SSI, MSI, LSI and VLSI.

(b) Define the terms fan-out, fan-in, Propagation delay and noise margin of a

logic-family. [8+8]

3. Explain about different spice – parameters of MOS transistor and their significance.

[16]

4. Explain about Pseudo-logic and draw the circuit topology of a three-input NOR

gate designed in Pseudo – NMOS. [16]

 

5. Explain the delay calculation procedure for CMOS inverter.

 

6. Discuss clearly about the following system Design principles.

(a) Pipelining

(b) Data-paths

 

7. Explain clearly the global routing phase of the floor planning of the chip with few examples by considering all constraints.

 

8. With suitable example explain any one of the routing algorithm

 

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