ASICs and FPGAs EC Syllabus for NIT Jalandhar
EC Syllabus for NIT Jalandhar
EC-360 ASICs and FPGAs [3 0 0 3]
Introduction: VLSI Design Flow, Structured Design Strategies, VLSI Design Styles, Chip Design Options.
Role of FPGAs, FPGA Type, FPGA vs Custom VLSI, FPGA Based System Design. Type of ASIC, Full
custom ASIC, Gate Array Based ASIC, Standard Cell Based ASIC, Different Types of Array, Design Flow, Case Study, Economics of ASIC.
ASIC Library Design: Transistor as Resistor, Transistor Parasitic Capacitance, Logical Effort, Predicting
Delay, Logical Area, Logical paths, multistage cells, Optimum Delay, Library Cell Design, Library
Programmable ASICs: Anti fuse, Static RAM, EPROM & EEPROM, Practical Issues, Specification and
FPGA: FPGA Architectures, SRAM-Based FPGA, Permanently Programmed FPGAs, Chip I/O, Circuit
Design of FPGA fabrics. ASIC I/O Cells
HDL: An overview of VHDL and verilog HDL, Basic concepts of hardware description languages. Structural, Data-flow and Behavioral styles, Delay modeling. Control statements, FSM modeling of hardware description.
Architecture of event driven simulators.
Logic synthesis – physical design compilation, simulation, and implementation. Floor planning and placement, Commercial EDA tools for synthesis.
1. 1.J. Bhaskar, “VHDL Primer”, Pearson Education Asia 2001.
2. Z. Navabi, “VHDL”, McGraw Hill International Ed. 1998.
3. S. Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Prentice Hall NJ, USA),
4. Michad John, Sebastian Smith “Application Specific Integrated Circuit”,Pearson Education, LPE
5. Wayne Wolf, “FPGA- Based System Design”Pearson education,LPE 1st Indian Reprint, (2005)
6. John V. oldfield,Richard C. Dorf “Field Programmable Gate Arrays” John Wiley & Sons (1995)