MODEL QUESTION PAPER
B.E / B.Tech. Degree Examinations
IF 245 COMPUTER ARCHITECTURE
Time: 3 Hours Max Marks: 100
Answer all questions
PART – A
(10 x 2 = 20 Marks)
1. What values remain on the stack after the following sequence of instructions are executed in a stack-based processor? The values 1 to 5 are stored in locations 1 to 50.
2. Where are the auto-increment and auto-decrement instructions useful?
3. For each of the following IEEE single-precision floating point numbers, explain
what type of number they represent.
(i) 0b0111 1111 1000 1111 0000 1111 0000 0000
(ii) 0b0000 0000 0000 0000 0000 0000 0000 0000
(iii) 0b0100 0010 0100 0000 0000 0000 0000 0000
(iv) 0b1000 0000 0100 0000 0000 0000 0000 0000
4. How is branch address modification achieved using the Bit-ORing technique in a micro-programmed control unit?
5. Suppose a DRAM has a RAS-CAS delay of 45 ns, has a CAS-data delay of 35 ns,
and requires a pre-charge time of 20 ns. If the DRAM does not support page mode
and returns 4 bits of data from each memory reference, what is its latency for read
operations, throughput and bandwidth?
6. Consider a three-level cache with access times of 5 ns, 20 ns, and 80 ns respectively. If the hit rates are 95%, 85% and 75% respectively in the three
caches, what is the average access time?
7. Vector processor is essentially processor. True/False. Give reasons for your
8. A program loop ends with a conditional to the beginning of the loop. How would
you implement this loop on a pipelined computer that uses delayed branching
with one delay slot? Under what conditions would you be able to put a useful
instruction in the delay slot?
9. How does a system with n-modular redundancy work? How fault tolerant is it?
10. List 3 unique features in the SPARC architecture.
PART – B
(5 x 16 = 80 Marks)
11a. Consider designing a pipeline for a DMA controller. What would be the various stages of the pipelines? Can you obtain any advantage? Explain (6 Marks)
b. Design the memory system (512 MB) for a processor with 3 memory ports for read and write (i.e it can simultaneously read and write 3 operands), whose access time is 3 times the processor clock period. Comment on the suitability of your memory system for efficient access with vector processors, or add features to your design to make it suitable. Clearly indicate the option that you have considered, and justify every choice that you have made. (10 Marks)
12a. i) A new microprocessor is designed with a conventional architecture employing single-address instruction and 8-bit words. Due to physical size constraints, only eight distinct opcodes are allowed. The use of modifiers or the address field to extend the opcodes if forbidden. (a) Which eight instructions would you implement? Specify the operations performed by each instruction as well as the location of its operands. (10 Marks)
ii) Demonstrate that your instruction set is functionally complete in some reasonable
sense; or describe an operation that cannot be programmed in your instruction set.
12b. i) Give the structure of 0-operand, 1 operand, 2-operand, and 3-operand instruction
formats. What are the typical instructions for which each of them is suited? How
are these handled in different processor architectures? (8 Marks)
ii) Consider executing the function C ← Sum of Ai * Bi for all I = 1 to n.
Write the code to implement this on a single-accumulator processor. Does this look like an efficient way of implementing this function? Which addressing modes would you use – if you had a choice. Which architecture would be better suited for this kind of operation? (8 Marks)
13a. Design a microprogrammed control unit for a multiplier (using shift-add operations). Give the complete design. (16 Marks)
13b. i) Explain the design of a pipelined floating point adder/subtractor. (10 Marks)
ii) A BGT (Branch if > 0) machine instruction has the expression Z+(N+V) = 0 as its
its branch condition, where Z, N and V are the zero, negative and overflow condition flags respectively. Write a micro-routine that can implement this instruction. Show the circuitry needed to test the condition codes. (6 Marks)
14a. i) A byte-addressable computer has a small data cache capable of holding eight 32 bit words. Each cache block consists of 1 32-bit word. When a given program is
executed, the processor reads data from the following sequence of hex addresses –
200, 204, 208, 20C, 2F0, 200, 204, 218, 21C, 24C, 2F4. The pattern is repeated 4 times.
Assuming that the cache is initially empty, show the contents of the cache at the end of each pass, and compute the hit rate for (A). Direct mapped cache (B). 4-way set associative cache. (10 Marks)
ii) Compare program controlled I/O with interrupt based processing of I/O. In which cases are the two schemes more suitable? (6 Marks)
14b. i) A 1024 x 1024 array of 32-bit numbers is to be normalized as follows. For each column, the largest element is found, and all elements of that column are divided by that maximum value. Assume that each page in the virtual memory consists of 4K bytes, and that 1M bytes of main memory are allocated for storing data during this computation. Assume it takes 40 ms to load page from the disk into tha main memory when a page fault occurs. How many page faults would occur if the elements were stored in row order? How many would occur if they were stored in column order? Estimate the total time needed to perform the normalization in both cases. (10 Marks)
ii) How is arbitration for the bus handled during DMA? (6 Marks)
15a. i) Discuss the various techniques used to handled control hazards in a pipelined processor. (10 Marks)
ii) Discuss the various fault-tolerance techniques used. (6 Marks)
15b. i) Consider the following sequence of instructions.
Add #20, R0, R1
Mul #3, R2, R3
AND #$3A, R2, R4
Add R0, R2, R5
In all instructions the destination is given last. Initially registers R0 and R2 contain 2000, and 50 respectively. These instruction are executed on a 4-stage pipeline. Show the sequence of operations using a pipe-line timing diagram. Explain each step. Give the contents of the interstage buffers B1, B2, and B3 during clock cycles 2 to 5. (10 Marks)
ii) Differentiate between RISC and CISC processors. (6 Marks)