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VTU eNotes On CMOS VLSI Design (Electronics and Communication)

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Publisher VTU eLearning
Author: Panel Of Experts
Number of Pages 213
Available in all digital devices
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The present chapter first develops the fundamental physical characteristics of the MOS transistor, in which the electrical currents and voltages are the most important quantities. The link between physical design and logic networks can be established. Figure 2.1 depicts various symbols used for the MOS transistors. The symbol shown in Figure 2.1 a is used to indicate only switch logic, while that in Figure 2.1 b shows the substrate connection.
Figure 2.1 Various symbols for MOS transistors This chapter first discusses about the basic electrical and physical properties of the Metal Oxide Semiconductor MOS transistors. The structure and operation of the nMOS and pMOS transistors are addressed, following which the concepts of threshold voltage and body effect are explained. The current-voltage equation of a MOS device for different regions of operation is next established. It is based on considering the effects of external bias conditions on charge distribution in MOS system and on conductance of free carriers on one hand, and the fact that the current flow depends only on the majority carrier flow between the two device terminals. Various second-order effects observed in MOSFETs are next dealt with. Subsequently, the complementary MOS CMOS inverter is taken up. Its DC characteristics, noise margin and the small-signal characteristics are discussed. Various load configurations of MOS inverters including passive resistance as well as transistors are presented. The differential inverter involving double-ended inputs and outputs are discussed. The complementary switch or the transmission gate, the tristate inverter and the bipolar devices are briefly dealt with.
2.1.1 nMOS and pMOS Enhancement Transistors
Figure 2.2 depicts a simplified view of the basic structure of an n-channel enhancement mode transistor, which is formed on a p-type substrate of moderate doping level. As shown in the figure, the source and the drain regions made of two isolated islands of n -type diffusion. These two diffusion regions are connected via metal to the external conductors. The depletion regions are mainly formed in the more lightly doped p-region. Thus, the source and the drain are separated from each other by two diodes, as shown in Figure 2.2. A useful device can, however, be made only be maintaining a current between the source and the drain. The region between the two diffused islands under the oxide layer is called the channel region. The channel provides a path for the majority carriers electrons for example, in the n-channel device to flow between the source and the drain. The channel is covered by a thin insulating layer of silicon dioxide SiO2 . The gate electrode, made of polycrystalline silicon polysilicon or poly in short stands over this oxide. As the oxide layer is an insulator, the DC current from the gate to the channel is zero. The source and the drain regions are indistinguishable due to the physical symmetry of the structure. The current carriers enter the device through the source terminal while they leave the device by the drain. The switching behaviour of a MOS device is characterized by an important parameter called the threshold voltage Vth , which is defined as the minimum voltage, that must be established between the gate and the source or between the gate and the substrate, if the source and the substrate are shorted together , to enable the device to conduct or "turn on" . In the enhancement mode device, the channel is not established and the device is in a non-conducting also called cutoff or sub-threshold state, for . If the gate is connected to a suitable positive voltage with respect to the source, then the electric field established between the gate and the source will induce a charge inversion region, whereby a conducting path is formed between the source and the drain. In the enhancement mode device, the formation of the channel is enhanced in the presence of the gate voltage.
Figure 2.2 Structure of an nMOS enhancement mode transistor. Note that VGS Vth , and VDS 0. By implanting suitable impurities in the region between the source and the drain before depositing the insulating oxide and the gate, a channel can also be established. Thus the source and the drain are connected by a conducting channel even though the voltage between the gate and the source, namely VGS 0 below the threshold voltage . To make the channel disappear, one has to apply a suitable negative voltage on the gate. As the channel in this device can be depleted of the carriers by applying a negative voltage Vtd say, such a