Electronics And Communication Test Preparations On Flip-Flops and Timers Part 1

Test Preparation on Electronics And Communication Test Preparations On Flip-Flops and Timers Part 1

1.

Which of the following is correct for a gated D-type flip-flop?

1The Q output is either SET or RESET as soon as the D input goes HIGH or LOW.
2The output complement follows the input when enabled.
3Only one of the inputs can be HIGH at a time.
4The output toggles if one of the inputs is held HIGH.

2.

When both inputs of a J-K flip-flop cycle, the output will:

1be invalid
2not change
3change
4toggle

3.

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

1asynchronous operation
2low input voltages
3gate impedance
4cross coupling

4.

The 555 timers can be used in which of the following configurations?

1astable, monostable
2monostable, bistable
3astable, toggled
4bistable, tristable

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