WBUT Question Papers Vlsi Circuits And Systems B Tech 6th Sem 2011

                                WBUT Question Papers Vlsi Circuits And Systems B Tech 6th Sem 2011

 

Time Allotted : 3 Hours

Full Marks : 70

The figures in the margin indicate full marks.

Candidates are required to give their answers in their own words

as Jar as practicable.

GROUP – A ( Multiple Choice Type Questions )

1. Choose the correct alternatives for any ten of the following :

i)              What is the intermediate step between circuit design and fabrication in VLSI ?

a)             logic design

b)             physical design

c)             functional representation

d)             system specification.

ii)            Channel less gate array is a sub type of

a)              standard gate ASIC b) configurable ASIC

c)             full custom ASIC d) gate array ASIC.

m MWT taterC°nneCfl0n       be done between

neighbouring modules means

31OCality                                  b) regularity

O modularity                         d) synthes(s

IV) Why band bending in MOSFET structure occurs ?

a)           difference of work function

b)           natural phenomena

c)            due to application of electric field

d)           none of these.

*

V) An                         ideal Co„stant current source gjves a current ^

200 mA, for a load resistance of 500 Q when it is short circuited, the current is

3) 40mA                                      b) 50mA

C) I00mA                                   d) 200 mA.

vl) A MOS diode cannot be used as a component of

a)      current mirror    b, rectifier circuit

O level translator                   d) current sink.

VU) In a CMOS Inverter circuit which of the following wifi act as driver ?

a)           depletion type PMOS

b)           depletion type NMOS

c)            enhancement type PMOS

d)           enhancement type NMOS.

viii)     To implement the Boolean function F = (A + B).(C + D)

using Pseudo NMOS logic design number of transistor required is

a) 3                                                b) 4 t

c) 5                                                 d) 6.

ix)         The model parameter LAMDA ( K ) in a MOS structure stands for

a)           flicker noise coefficient

b)           transit time

c)           channel length modulation

d)           transconductance.

x)           Frequency compensation for an OP-AMP can be achieved by

a)           increase gain

b)           adding zero

c)           minimize overall phase shift

d)           none of these.

xi)         The expression for body – effect coefficient in MOSFET is

a)           ( 2qNA esi ) 1/2 / Cox.

b)           ( 2qNA esi) / Cox.                                 .

c)              ( 4qNA esi ) 1/2 / Cox.

d)           ( 4qNA esi) / Cox.

xli) The expression of low noise margin ( NML ) in MOSFET is

a)        VIL – VOL                           b) VOL – Vjl

c)    VOH – VIH                          d) VIH – V0h •

,xiii) For 0-25 urn process what is the value of K ?

a)        0-5 |^m                          b) 0125 j^m

c)   0-75 |um                        d) 1 [im.

xiv)      Soft node leakage problems of CMOS NORA structure can be reduced using

a)           TSPC logic

b)          Zipper CMOS logic

c)           NM logic

d)          Cascaded domino logic.

xv)        Which domain is not included in three domains of Y chart ?

a)           system specification b) structural

c)           geometrical layout d) beavioural.

xvi)      Latch up occurs for CMOS as

a)           CMOS invariably picks up stray signal

b)          unavoidable existence of npn, pnp transistors embedded in CMOS

c)           absence of parasitic effect

d)          CMOS has low power dissipation.

3404                                             4

( Short Answer Type Questions )

Answer any three of the following.           3×5= 15

  1. a) Draw the flow chart of VLSI design flow and explain.

b)           What are the different design rules ? Discuss each in brief.

  1. Explain how a combination of switches and capacitors can be used to emulate a resistor.
  2. What are the advantages of dynamic CMOS logic having precharge and evaluate phase ?
  3. a) What do you mean by CMOS transmission Gate ( TG ) ?
  4. b)           Design the following circuits using transmission gates

i)               Half adder

ii)             D flip-flop.

  1. Why is reference voltage required in IC ? What are the criteria for a good reference voltage source in a VLSI circuit ?                         2 + 3

GROUP -C ( Long Answer Type Questions )

Answer any three of the following. 3 x 15 = 45

  1. a) What do you mean by rise time (tr), fall time (tf) and delay time (td) ?

b)          Prove that Wp ( channel width of P-MOS ) ~ 2 5 Wn ( Channel width of N-MOS ).

c)          Explain Dynamic CMOS Logic and Domino CMOS Logic with suitable diagram.

  1. a) Write the basis steps of fabrication.

b)          Describe the n-well fabrication process with a suitable diagram.

c)           Draw the schematic diagram of Y ~ {A + B )■{€ + D )

  1. a) What is static and dynamic power dissipation in a MOS

circuit ?

b)          What is routing capacitance in a MOS ? Deduce switching characteristics rise time, fall time and delay time of an inverter circuit.

10. a) Explain the basic building block of FPGA with diagram.

b)             What is PLA ?

c)              Implement /,(a, b, c) = Im(3, 5, 6, 7) and Ji{ac) “ 2m(0, 2, 4) using PLA.

d)               Explain the design flow of an ASIC.

X 1. Write short notes on any two of the following :

a)              FPGA

b)             Design rule checker ( DRC )

c)              Phase locked loop

d)             Comparator *

e)             ASIC            L

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