WBUT Question Papers EE Vlsi Circuits And Systems B Tech 6th Sem 2012

WBUT Question Papers EE

Vlsi Circuits And Systems B Tech 6th Sem 2012

Time Allotted : 3 Hours

Full Marks : 70

The figures in the margin indicate full marks.

Candidates are required to give their answers in their own wordS

as far as practicable.

GROUP – A ( Multiple Choice Type Questions )

1 • Choose the correct alternatives for any ten of the following :

i) The noise margin for high signal levels j NM j is 3) VIL~Vol                                     b) V

L OL                    ‘                        OH IH

C) V0H ~ VOL                                       d* n°ne 0f these


il) The switching ‘threshold voltage of CMOS inverter is obtained when

a) V, –V t                                     b) V = – y

ln out                                         T.n           T.p

C) Vin = 2Vout                                       d) none of ^ese.

iii) In CMOS static logic design, total number of transistors . required for the Boolean function F = A + ( B + CD ) is

a) 10                                        b) g

d) none of these.

iv)          The sum-of-product expression of a Boolean function can be realized by

a) AOI gates                            b)

c) both (a) and (b)                    d)

v)           Dynamic logic circuit is

a)            faster than static design

b)           slower than static design

c)            bigger than static design

d)           none of these.

vi)          VHDL is used for a)                 Timing analysis   b) c)  logic design d)

vli) Active resistor is used for

a)            less fabrication area

b)           load resistor

c)            constant current source

d)           all of these.

viii)      For depletion,type NMOS

a)            the threshold voltage is + ve

b)            the threshold voltage is – ve

c)            the threshold voltage is – ve and + ve

d)           all of these.

ix)         BiCMOS means

a)            two BJT circuits

b)            two CMOS circuits

c)            both BJT and CMOS circuits

d)           none of these.

x)           For a symmetrical CMOS inverter the relation between aspect ratio of NMOS and PMOS is

a)            (W/L)p = (W/L)n b) (W/ L)p – 2 • 5 [W/ L)n

c)             (W/L)n =2-5 [W/L)p d) (W / L)p = 5 (W / L)n .


xi)          Pseudo riMOS logic provides which of the following advantages ?

a)            Static power dissipation is less compared to CMOS logic

b)            It is faster compared to other logics

c)            It requires less no. of transistors compared to CMOS logic

d)            It is more noise immune.

xii)        Configurable logic blocks are used in

a)            gate array design style

b)            standard cell based design

c)            field programmable gate array layout

d)           full custom design.

GROUP -B ( Short Answer Type Questions )

Answer any three of the following.

  1. What is current source and current sink in VLSI circuit ? Design a current sink using VDD = -Vss- 2 • 5V to sink a current of lO^A. Estimate the minimum voltage across the current source and the output resistance. Assume

Kp =50mA/V2, L = 5[xm. VTHN=0 83V, X = 0 06. 2 + 3

  1. Draw and explain the operation of MOS Switched Capacitor Integrator and also find the expression for output voltage.
  2. Compare between static logic and dynamic logic. Explain the operation of Domino-logic to design any CMOS circuit. 2 + 3
  3. What is Transmission Gate (TG) ? Explain the operation of Edge Triggered D Flip-Flop using CMOS TG gates. Implement the expression using CMOS TG logic. Z = XY1 + XY.
  4. {X 1 = complement of X )                                                  1+2 + 2
  1. Draw the circuit of a CMOS full adder circuit and explain its operation.

GROUP -C ( Long Answer Type Questions )

Answer any three of the following. 3x,5 = 4c

7– a) Explain the fabrication process sten« f

transistor with necessary diagrams                            “ NM°S

b)            Write down the difference between twin ,„h

P-well process.                                       twm-tub process and

O Draw the layout of the following :

8 | „ F=ab + CD (u)f- = A + SC

a’                                          ~,c. or

and clearly define oneraur,^

CMOS inverter

PMOS.                           operating regions of NMOS and

b)            Show that for a symmetric CMOS inverter the t

margins are same and are eaual m m ,                                nolse

for ideal CMOS inverter (W/L)p _ 2 5 (W/ ^n^

9. a) What is CMRR ?

di^entiallmplifier01^1111 diagram’ °Peration of a

^ heTp^aSdla^am4 ^ °f °PAMP With

10‘ S ru mean by current stak – ™t?6

and capacit°rs cj What is phase locked loop ? Fxni^in ■+

Mention two uses of phase locked looj,                        °Pera»on.

11 ^nte Sh°rt n°tes on any thr?e of the following ;  aJ Constant voltage scaling

b)             CMOS NORA logic cJ ASIC

d)            DCVSL and pseudo n-MOS inverter.

Leave a Comment