WBUT Question Papers EE Vlsi Circuits And Systems B Tech 6th Sem 2010

WBUT Question Papers EE

Vlsi Circuits And Systems B Tech 6th Sem 2010

 

Time Allotted : 3 Hours

Full Marks: 70

The figures In the margin Indicate Juil marks.

Candidates are required to give their answers in their own words

as Jar as practicable.

GROUP-A (Multiple Choice Type Questions )

  1. Choose the correct alternatives for any ten of the following:          10×1 = 10

1) Scaling is done for

a)            improving the switching speed

b)            reducing the power dissipation

c)             decreasing the chip size

d)            all of these. ‘         .

ii) For 0*25 process what is the value of X. ?

a) 0*5 pin                    b) 012^ |im

c) 0-75 |xm         d) 1 (im.

lit) The two transitional critical points on the VTC curve are identified where the slope becomes

a)   -1               b) + 1

C) 0     ‘          d) 00. V

iv)           Noise margin for low signal levels (NMH) is a> vu.-Vol    b) Vm -Va °y VtmrYm d) voh ~ vn •

v)             The threshold voltage of an enhancement nMOS transistor is     –

a)    greater than 0 V b) less than OV

c)   equal to 0 V  d) none of these.

vi)           The (W/L) ratio of the pMOS and nMOS transistors for an ideal symmetric inverter is

a)         1        b) 3-5

c)        2-5     d) 4.

Vii) The equivalent (W/L) of two nMOS transistors with (Wy/L) and (W2/L) connected in parallel is

a> (w,/l)+(w2/l) b) (wyL^uyL) c) l/(t/w,+x/w2) dr (WyLj/fWyL).

viii)       In MOSFET threshold voltage depends on

a)        gate voltage  b) source voltage

c)        drain voltage d) all of these.

ix)        In a short channel MOS structure electron mobility

a)             increases

b)             decreases

c)             remains same

d)             first increases then decreases.

x)          CMOS inverter is useful because it has

a)             low sensitivity to noise

b)             low power consumption ‘

c)             excellent speed

d)             all of these.

xi)        The main advantage of precharge-evaluate dynamic logic is

a)             lesser number oftransistors required

b)             high Speed

c)             low power consumption

d)             all of these.

xii)      When two nMOS are connected in parallel, the

i equivalent fc„ is given by

a)  2kn                b) kJ2

, c) fcn               d) none of these.

xiii)      How many transistors are required to design the function F-(ABC+DE)’ using CMOS logic ?

a)        5     b) 7

c)         lb   d) 14. ,

xiv)      In the region C of the VTC curve of CMOS inverter

a)            pMOS is linear & nMOS is In saturation

b   pMOS is In saturation & nMOS is In linear

c)  pMOS is In saturation & nMOS is in saturation

d)            pMOS is In linear & nMOS is in linear.

xv)        A MOS device can be used as a resistor

a)      in linear region    b) in saturation region,

c)   sub-threshold region d) none of these.

GROUP-B (Short Answer Type Questions)

Answer any three of the following. 3 x 5 = 15

  1. a) Explain the VLSI design flow with the help of y-chart.

b)           Discuss the concepts of regularity, modularity and locality in VLSI design.

  1. Draw the VTC curve of a simple CMOS inverter circuit and clearly define the different operating regions of NMOS and PMOS.
  2. Describe the following phenomena in MOS structure :

a)            I-V characteristics

b)        Channel length modulation

  1. a) What do you mean by CMOS Transmission Gate (TG ).
  2. b)  Design the following circuits using transmission

gates

i)                 2 input XOR gate

ii)               2 x 1 MUX.

  1. Explain with a circuit diagram, operation of a differential amplifier.

GROUP-C ( Long Answer Type Questions )

Answer any three of the following. 3 x 15 = 45

  1. a) Design a transmission gate lull adder circuit and

explain.

b)            What are the differences between PLA and PAL ?

c)             Implement the following two functions using PLA and

PAL

i)                 FI = BA + C’b’A + CB’a’

ii)               F2 = C’b’A1 + CBA.

  1. a) Where are the dynamic logic circuits preferred in

comparison to static logic ?

b)            What is domino CMOS logic ? How the cascading problem in dynamic logic can be eliminated in domino logic ?

c)             What is the charge sharing problem in dynamic CMOS logic ? How can it be prevented ?

d)            Describe the operation of three transistor DRAM cell.

  1. a) What are the differences in between diffusion and ion

implantation ?

b)            Explain the fabrication steps of CMOS inverter with necessary diagrams.

  1. a) Show that for a symmetric CMOS inverter the two noise

margins are same and are equal to VIL. Also show that

for ideal CMOS inverter (W/L)p =2-5(W/L)„.

b)            What do you mean by design rules ? What are the differences in between lambda ( X ) and micron ( n ) rules.  10 + 5

11. Write short notes on any three of the following :

a)             Constant voltage scaling

b)             CMOS NORA logic

c)             Drain Induced Barrier Lowering ( DIBL )                                    .

d)                                 CPLD

e)             Dynamic RAM

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