WBUT Question Papers EC Digital Electronic Circuits B Tech Forth Sem 2011

WBUT Question Papers EC

Digital Electronic Circuits B Tech Forth Sem 2011

Time Allotted : 3 Hours

FuU Marks . 7Q

The figures in the margin indicate full marks. Candidates are required to give their answers in their own words

as far as practicable.

GROUP – A ( Multiple Choice Type Questions )

  1. Choose the correct alternatives for any ten of the following :

10 x 1 – 10

i)  The Excess-3 representation of decimal 59 is ”

. a) 01100010 b) 00111110

c) 10001100                            d) none of these.

ii)              The number of full address required to construct an m-bit parallel adder is

a)        m/2       b) m – 2

c)           771     d) m + 1.

 

iii)         The 2’s complement representation of ( -19 )io is

a) 101100                              b) 101110

c) 101101                               d) none of fchese.

iv)         The maxterm corresponding to decimal 9 is

a) AB’C’D                                   b) A + B’ + C’ + D

c) A’ + B i C + D’                  d)


The number of comparators requ ired in a 8-bit flash type A/D converter is

vi)         A 3-bit synchronous counter uses flip-flops with propagation delay of 20 ns each. The maximum possible time required for change of state will be

a)       60 ns  b) 40 ns

c)        20 ns   d) none of these.

vii)        The number of EX-OR gates required for the conversion of 1 1011 to its equivalent Gray code is

a) 2                                       b) 3

c) 5                                       d) 4.

viii)      A mod-2 counter followed by a mod-5 counter is

a)           same as a mod-5 counter followed by a mod-2 counter

C

b)           a decade counter

c)           a mod-7 counter

d)           none of these.

ix)         Which family has better noise margin ? a) ECL    b) DTL c) TTL d) MOS.

x)           The number of D flip-flops required to design a mod-10 ring counter is

a) 5                                       b) 10

c) 9                                       d) 8.

 

xi)          A two-input EX-OR gate can be used as an inverter when one of its inputs is kept at logic

a) 0                                         b) 1               ? ;

c) either 0 or 1                         d) none of these.

xii)        If the resolution of a D/A converter is approximately 0-4% of its full scale range, it is

a)            an 8-bit converter b) a 10-bit converter

c)             a 12-bit converter d) a 16-bit converter.

GROUP -B ( Short Answer Type Questions )

Answer any three of the following.                3×5= 1

  1. Design a Full Adder circuit using a decoder and other necessary logic gates. Assume that the decoder has all active low outputs.                        5
  2. Design a S-R flip-flop with the help of J-K flip-flop.                         5
  3. Implement a 16:1 MUX by using 4 : 1 MUX only.
    1. a) Distinguish between synchronous and Asynchronous counters. 2

b)            Calculate the frequency of 4-bit ripple counter, if the . period of waveform at the last flip-flop is 64 microsecond.                3

  1. Design a Binary to Gray code converter using PROM.          5

GROUP -C ( Long Answer Type Questions )

Answer any three of the following. 3 x 15 = 45

%

  1. a) Design a sequential circuit that implements the following state diagram. (Use D flip-flop)                                                 10

I

b) Implement the following Boolean function using

 

8 : 1 MUX:

F(A, B, C,D) = £m( 0, 7, 8, 9, 10, 11, 15 ).                           5

. a) Design a MOD-6 synchronous up-counter using J-K flip-flops.                                                                                        y

b) Implement the following function using 3x4x2 PLA • Fi(A3C) = Xm(3,5,6,7) F2( A B, C ) = 1(0,2,4,7). 8

  1. a) Simplify the following function in SOP form using Quine

MC- Cluskey method :

F(A,B,C,D)=1m( 0,1,4,7,9,11,13,15) + £d(3,5).             9

b) Describe the operation of a two-input NAND gate constructed with CMOS.                                      6

  1. a) Design a combinational circuit for Excess-3 code to

BCD conversion using minimum number of logic gates.

b)           Describe the principle of operation of successive Approximation type AjD converter.                              a

  1. Write short notes on any three of the following :                                   3 x £

a)             4-bit magnitude comparator

If

b)             Bi-directional shift register

c)              PAL                                                -y’

d)             Master-slave J-K flip-flop

e)             EEPROM.

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