# WBUT Exam Papers CS Digital Electronics And Logic Design

# B Tech Third Sem Dec 2006

( Full Marks : 70Group – A (Multiple Choice Questions)

Choose the correct alternatives for any ten of the following questions :

a) A full adder circuit can be designed using 1) a half adder & an OR gate

ii) a half adder & an AND gate 111) two half adders & an OR gate iv) none of these.

b) The fastest logic family is

1) TTL ii) CMOS

Hi) RTL iv) ECL.

c) For a parallel in parallel out shift register we need I) 1 ii) n

ill) 2n + 1 iv) n + 1

clock pulse/pulses.

d) The number of Flip-Flops required to design a MOD-18 counter is i) 3 ii) 4

iii) 5 iv) 6.

The maximum positive number that can be represented in l’s complement representation is

1)

2 ^{n_1} – 1 ii) 1 -2^{n_1} UU _ (2 ^{1} – l) tv)

n- 1

CS/B.Tech/SEM-3/EC-312/06

f) Flip-Flop has

i) one stable state

111) no stable state The fastest ADC is

1) dual slope 110 parallel comparator

14 ■ two stable states Iv) none of these.

11) successive approximation iv) none of these

The minimum number of NAND gates required to implement an EX-OR gate is 1) 2 ID 3

ill) 4 iv) 5. 1

According to Boolean algebra which of the following relations is not valid ?

I) X ( Y, Z) = (XY) Z U) X ( Y + Z ) = XY + XZ ill) X + XZ = X iv) X (X + Y) = 1.

The figure of merit of a logic family is given by ^ gain bandwidth product

II) propagation delay time x power dissipation Hi) fan-out x propagation delay time tv) noise margin x power dissipation.

PROMs are used primarily for

I) data storage

II) temporaiy program and data storage

ill) they are inexpensive

iv) permanent program & data storage.

The decimal 37 is represented in BCD by 1) 100101 U) 00111011

ill) 00100101 iv) none of these.

Group -B (Short Answer Questions)

Answer any three questions. 3×5*15

- Perform the arithmetic operation ( – 25 )
_{l0}+ ( – 15 )_{10}in sign 2’s complement method, Assume 1-bit sign and 6-bit information. - Minimize the following expression using K-map and realize the simplified expression using NAND gates only.

G (A, B, C, D ) = X ( 1, 2, 3, 5, 6. 11, 12 ) + D ( 7, 8, 10, 14 )

- Implement a full adder circuit using decoder.
- Implement a clocked JK flip-flop using NAND gates only.
- Implement the following function using 8 : 1 MUX :

F (A, B, C, D ) = I ( 0, 2, 4, 8. 9, ( 10, 11, 12, 13, 14, 15 )

Group – C (Long Answer Questions)

Note: Answer any three of the following questions.

a) Distinguish between ROM, PLA and PLD’s as elements realising Boolean functions. q

b) Design a combinational circuit using an 8 x 4 ROM that accepts a 3-bit number and generates an output binary number equal to the square of the Input number.

6

c) Draw logic diagram of Master/Slave JK flip-flop. Why is it called so ? 3

a) Write down the excitation table of JK and D flip-flops. Derive the excitation equations for these two flip-flops. 3 + 3

b) Design a 4-bit Up/Down asynchronous counter using all JK flip-flops and other necessary logic gates. Use one direction control input M. If M = 0, the counter will count up and for M = 1 the counter will count down. 9

- a) Describe the operation of successive approximation type A to D converter. How

many dock pulses are required |n worst case for conversion for an 8-bit SAR ? Define quantizing error for an ADC. 6+1 + 1

b) Draw a neat diagram for a R-2R ladder type DAC. What is linearity error and offset error in a DAC ? , 5+1 + 1

- a) Draw the circuit for a four-bit Johnson counter using D flip-flops and explain its
_{L}

operation. Draw the timing diagram for this 4-bit Johnson counter. How does this timing diagram differ from that of a Ring counter ? 8 + 2 + 2

b) Perform the conversion from D flip-flop to JK flip-flop. 3

- Write short notes on any three from the following : 3×5=15

a) Content Addressed Memoiy

b) Tri-state gates in TTL family

c) BCD-to-7 segment decoder/driver

d) Data lock-out in a counter.