VTU Previous Year Question Papers EC 3rd Semester Logic design July 2008
VTU Previous Year Question Papers EC 3rd Semester
Logic design July 2008
Note : Answer any FIVE full questions.
1 a. Show that EX-OR operation is not distributive over AND operation.
b. State and explain the Shannon’s Reduction theorem.
c. Find the conjuctive and Disjunctive canonical forms of the expression: F(ABC) = AC + BC’
d. Realize the EX – NOR function using only minimum number of i) Nand Gates Gates.
2 a. Define i) Subsume ii) Prime implicant iii) Essentia prime impiicant. Give an example for each.
b. Find the minimal conjunctive normal form for f(ABCD) = A (^)B (^) C Q D. Use K maps for specification.
c. For the given Boolean function, determine a minimal sum using variable entered maps where x, y and z are map variables.
f (ABxyz) = A x y z + A x y z + A x y z + B x y z + B x y z + x y z + x y z
3 a. Design a 4 input one output minimal gate combination network using only NAND GATES which has a 0 output when the majority of its inputs are at logic 1 and a 1 output when the majority of its inputs are logic 0. When the number of l’s and 0’s are equal consider it as a don’t care output.
b. Design a stage of one Bit comparator which when cascaded helps in comparing two Binary numbers of any bit length. Draw the logic diagram.
4 a. Design a full subtractor using 3 to 8 Decoder and Nand gates.
b. Realize the two expression given fi(x y z) =^m(l, 2, 3, 7) and f^(x y z) “5]m(0, 1, 2, 6). using PLA of the smallest size and draw the PLA table.
5 a. What are the disadvantages of Totempole output? Draw and explain the logic diagram of a circuit, which removes the above disadvantage.
b. Give a detailed comparison among LSTTL CMOS and ECL logic families highlighting the advantages of each for a given application.
6 a. Draw a switch Debouncer using a SR latch and show the waveforms of switch Bounce and Debounce.
b. Explain the advantages of an edge triggered flip flop over a pulse triggered flip-flop.
c. Derive the characteristic equation of an SR flip flop and a JK flip flop.
7 a. Design a Modulo – 6 self correcting counter whose counting sequence is \0-1-4-6-7-5-0. Use JK Flip Flops for realization.
b. Draw the two forms of 3 bit shift register counters and explain their operation.
8 a. Distinguish between Mealy and Moore model of clocked synchronous sequential network with block diagrams.
b. State table shown refers to a clocked synchronous sequential network. Make a state assignment in binary code and find the excitation and output functions using JK flip flops.
Draw the logic diagrams.
|x- 0||x — 1||x = 0||x= 1|