# VTU Previous Year Question Papers EC 3rd Semester Logic design Dec 2007

# VTU Previous Year Question Papers EC 3rd Semester

# Logic design Dec 2007

**Note ; Answer any FIVE full questions.**

1 a.With suitable example explain:

i) Boolean function

ii) Maximum canonical formula

iii) Complete Boolean function.

b.Show the realization of the following:

i) NOR using NAND gates ii) X-NOR using NAND gates.

c. Draw the logic diagram using basic gates of the following Boolean function:

f(A, B,C,D)= a(b(CD + E)+ CE)+ A B assuming input variables are available in uncomplemented and complemented form.

2 a. Differentiate between positive, negative and mixed logic. Give example for each case.

b. Prove that: i) x + xy = x + y ii) ab + ac + abc(ab + c) = 1.

c. Simplify using Karnaugh map method and realize the simplified function using NAND gates. (x, y,z) = Σm(0,l,4)+ Σdc(3,7).

3 a. Design a minimal two level gate combinational network that detects the presence of six illegal code group in a 4-bit that represent 8421 BCD code, by providing logic 1 output.

b. Simplify the following switching function using Quine-Mccluskey method: f(A,B_{;}C,D)= Σm(l,3,13,15)+ Σdc(8,9,10,11).

4 a.Define: i) Propagation delay ii) Power-delay product iii) Fan-out iv) Noise margin.

b. Write the circuit diagram of a TTL NAND gate and draw and explain the transfer characteristic.

c. Explain with respect to TTL the following output stages:

i) Totem pole ii) Open collector iii) Tri-state output.

5 a. Draw the circuit of a JK-flipflop using NAND gates building blocks. Verify that JK-flipflop satisfy the difference equation: Q_{n+1} = J_{n}Q_{n} + K_{n}Q_{n} .

b. Show how JK-flipflop can be connected as i) D-flipflop ii) T-flipflop.

c. Describe a C-MOS inverter with relevant circuit diagram. Differentiate between ripple and synchronous counter.

6 a. Design a synchronous module-S counter and sketch the output waveform.

b. With a block diagram describe a 3-bit Johnson twisted ring counter. Draw the sequence diagram and indicate the valid and invalid states.

7 a. Discuss what is race – around in JK-flipflop and describe: i) Master-slave JK-flip-flop

ii) Edge triggered flipflop.

b. Design suitable circuit for the output of truth table shown in the table below using

i) 8:1 Multiplexer ii) 4:1 Mu

Inputs | Outputs | ||

A | B | c | D |

0 | 0 | 0 | 0 |

0 | 0 | I | 1 |

0 | 1 | 0 | 1 |

0 | 1 | 1 | 0 |

1 | 0 | 0 | 1 |

1 | 0 | 1 | 1 |

1 | 1 | 0 | 0 |

1 | 1 | 1 | 0 |

tiplexer. le following:

8 Write short notes on any three of the Following.

a) Priority encoder

b) CMOS in comparison with TTL family

c) Programmable arrav loeic.

d) Magnitude comparator