VTU Previous Year Question Papers BE CS Advanced Computer Architecture July 2011
VTU Previous Year Question Papers BE CS Eighth Semester
Advanced Computer Architecture July 2011
Note: Answer FIVE full questions, selecting at least TWO questions each from Part-A and Part -B.
PART – A
1 a. Explain with a learning curve, how the cost of processor varies with time along with factors influencing the cost.
b. Find the number of dies per 200cm wafer of circular shape that is used to cut die that is 1.5cm side and compare the number of dies produced on the same wafer if die is 1,25cm.
C. Define Amdahls Jaw. Derive an expression for CPU clock as a function of instruction count, clocks per instruction and clock cycle time.
2 a. What are major hazards in a pipeline? Explain data hazard and methods to minimize data h azard with example.
b. Consider the following calculations : x = y + z ; a = b c. Assume the calculations are done using registers. Show, using 5 stage pipeline, how many clock pulses are required for direct operations. By recording with stalls show how many clock pulses arc required and saving in the number of clock pulses to solve data hazard.
3 a. What are data dependencies? Explain name dependences with example between two instructions.
b. What is correlating predictors? Explain with examples.
C. For the following instructions, using dynamic scheduling show the status of R,O.R, Reservation station when only MUL.D is ready to commit and two L.D committed.
L.D F6, 32(R2)
L.D F2, 44(R3)
MUL.D F0, F2, F4
SUB.D F8? F2, F6
DIV.D F10. F0, F6
ADD.D F6, F8, F2.
Also show the type of hazards between instructions.
4 a. Explain the basic VLIW approach for exploiting ILP, using multiple issues.
b. What are the key issues in implementing advanced speculation techniques? Explain in detail,
C. Write a note on value predictors.
5 a. Explain the directory based cache coherence for a distributed memory multi processor system along with state transition diagram.
B. Explain any two hardware primitives to implement synchronization with example.
6. Explain block replacement strategies to replace a block, with example when a cache
B. Explain the types of basic cache optimization.
C. With a diagram, explain organization of data cache in the opteron microprocessor.
7. a. Explain the following advanced optimization of cache :
i) Compiler optimizations to reduce miss rate.
ii) Merging write buffer to reduce miss penalty.
iii) Non blocking caches to increase cache band width.
8 a. Explain in detail the architecture support for protecting processor from each other via virtual machines.
B. Explain internal organization of 64Mb DRAM.
9 a. Explain in detail the hardware support for preserving exception behaviour during speculation.
b. Explain the architecture of IA64 intel processor and also the prediction and speculation support provided.