VTU Previous Year Question Papers BE CS Eighth Semester
Advanced Computer Architecture Dec 2010
1 a. Discuss the evolution of computer architecture, with a suitable diagram.
b. Explain the vector super computer, with a neat diagram.
2 a. briefly explain the different types of data dependencies. For the following code segment, draw the dependency graph:
S1 : Load R1, A ; R1<-Mem(A)
S2 : Add R2, R1 ; R2 <- [R1 + [R2]
53 : Mov R1, R3 \ R1 <r-[R3]
54 : Store B, R1 ; Mem(B) <- [R1]
b. Compare control flow architecture and data flow architecture.
c. List the node degree, number of links and network diameter for the following:
i) Completely connected
ii) Binary tree
iii) 2D Mesh
iv) 2D Torus
3 a.Compare the super scalar processor and VLIW processor.
b. Consider the following interleaved memory design for a main memory system with 16 memory modules. Each module is assumed to have a capacity of 1 M byte. The machine is byte addressable.
Design 1 : 8-way interleaving with 2 memory banks.
Design 2 : 4-way interleaving with 4 memory banks.
i) Specify the address format for each of the above memory organizations.
ii) Determine the maximum memory bandwidth obtained, if only one memory module fails, in each of the above organizations.
c. Explain the overlapping register window mechanism of SPARC architecture.
4 a. With a neat diagram, explain the back plain bus.
b. Design a binary integer multiply pipeline with 5 stages. The first stage is for partial product generation. The last stage is a 36b carry-lookahead adder. The middle 3 stages are made of 16 carry-save adder of appropriate lengths.
i) Prepare a schematic design of 5-stage multiply pipeline. All line widths and inter-stage connection must be shown.
ii) Determine the maximal clock rate of the pipeline of the stage delays are ti = t2 = t3 -14 = 90 ns and ts = 45 ns. The latch delay is 20 ns.
iii) What is the maximal throughput of this pipeline in terms of the number of 36b results generated per second?
5 a. Indicate the factors that could cause delays in the instruction pipeline. For one of the listed factors, explain how the pipeline delay can be reduced.
b. Consider the following pipeline reservation table:
i) What are the forbidden tencies?
ii) Draw the state transition diagram.
iii) List all simple cycles and greedy cycle.
iv) Determine minimum average latency.
v) Find the optimal constant latency cycle.
vi) Determine the throughput of this pipeline, with clock period being 20 ns.
6 a. What is the cache-coherence problem? Explain Goodman’s write-once cache coherence protocol.
b. What is a barrier? Explain the hardware method of implementing the barrier.
7 a. In a supermarket, vendors would be interested in extracting the information on the item sets, the customers frequently purchase, using the large database, indicating set of items purchased in each transaction. Show how this information of frequently purchased item sets could be obtained. Explore the parallelism that exists in the process.
b. Write the parallel code for the simple equation solver, using the message-passing model.
8 a. With the necessary diagrams, explain the following types of message passing protocols:
b. What is meant by a scalable system? Explain any two types of scaling.