# Embedded System Design January 2008

Note : Answer any FIVE full questions.

1 a. Define an embedded system. Briefly explain its 3 characteristics that distinguish such systems from other systems. Write the block diagram of a digital camera.

b. Derive the formula for percentage revenue loss. If the lifetime of a product is 72 weeks, delay in time to market is 12 weeks, determine the percentage revenue loss. If NRE cost is \$100000, total number of units is 2000 and unit cost is \$250, determine the per product COSt.

c. Differentiate between SPP and ASIP.

20 a. Explain the top down design process used in design technology.

b.  Write and compare any two algorithms for GCD computation.

c.   Show how FSDM can be optimized for GCD computation for any one of the algorithms for GCD computation.

3 a.Define the following:

i)    Linker ii) Cross compiler iii) Latency

iv) Datapath v) Device driver            vi) Device programmer.

b. Describe the working of a PWM unit with timing diagrams. How it can be used for speed control of DC motor.

C. Explain pipelining technique. Determine the speedup of a pipelined processor over a non- pipelined processor if 4000 instructions are executed in an 8 stage pipelined processor whose clock frequency is 20 MHz.

4 a.     Given a 16 bit timer with 20 MHz,

i)    Determine its range and resolution

ii)   Calculate the terminal count value needed to measure 1.5 msec interval

iii)  If a prescaler is added, what is the minimum division needed to measure an interval of 50 msec. Determine its range and resolution, if the division value is a power of 2.

b.  Determine the resolution of an 8 bit ADC with an analog input voltage range of 0 to 5 V. Determine the digital encoding for 3.5 Volts using a formula and trace the steps using successive approximation technique. Write successive approximation technique. Write the steps for this technique in the form of a table, with necessary columns / informations.

c.   Write two differences between:

i)    ROM and R/w M

ii)   P SRAM and NVRAM

iii)  SRAM and DRAM.

5 a. Write block schematics to increase the number of bits in a memory and also to increase the number of memory locations. Compare 2 k x 8 ROMs into a 4 k x 16 ROM.

b.  Describe fully associative cache mapping technique. In a memory hierarchy design consisting of cache and main memory, the cache miss rate is 15%, cost of memory a* cess is 20 cycles and cost of cache access is 20 cycles and cost of cache access is 2 cycles. Determine the average cost of access.

c.   Explain the features of CAN bus and IEEE 802.11 protocols.

6 a. Describe shared data problem with an example and algorithm.

b.  Define interrupt latency. What are the 4 factors/parameters involved in it? Let the high, medium and low priority processes require an execution time of 150 jisec, 250 {.isec and 350 \xsqc respectively. If the interrupts are disabled for 200 jxsec and the deadline for the low priority process is 850 jisec, determine its worst case interrupt latency. Can it meet the deadline, if the other two interrupts occur? Illustrate with a timing diagram. (08 Marks)

c.   Describe round robin architecture with an example.

7 a. What are semaphores and critical sections? Explain P and V algorithms for locking and unlocking a resource for binary semaphore variable.

b.  Describe the function of a scheduler with a state transition diagram and the relationship between task and data.

c.   Explain the use of message queues with an example or algorithm.

8 a. Explain “encapsulating semaphores” with an algorithm.

b.  Describe the two rules that an RTOS environment must follow for interrupt routines.

c.   Explain how memory space can be saved in hard real time scheduling with an example.