VTU Previous Question Papers BE EC 8th Semester
Embedded System Design December 2010
Note: 1. Answer any FIVE full questions.
2. Standard notations are used.
3. Missing data may be suitably assumed.
1 a. What are the characteristics of an embedded system design? List the design metrics used to compare them.
b. Determine the revenue loss, if the product’s lifetime is 74 weeks and the delay in the market is 6 weeks. Derive the formula used for the calculation.
c. For a particular product, determine the NRE cost and unit cost to be the following for the three listed IC technologies:
FPGA ($ 10000, $50): ASIC ($50000, $ 10)
VLSI ($200000, $5)
Determine the precise volumes for which each technology yields the lowest total cost.
2 a. Develop an efficient algorithm for GCD. Convert it to FSMD and show the optimized FSMD.
b. With a neat diagram, explain the architecture of a general purpose processor.
3 a. Define the following:
i) Cross compiler ii) Emulator iii) Debugger iv) In circuit simulator
b. Differentiate between:
i) Single purpose and general purpose processors
ii) Harvard and von-Neumann architecture
c. Wfth a neat diagram, explain how the pulse width modulator works. What are the considerations in selecting the clock, the prescalar and the counter? Assuming an 8-bit up counter, calculate the count to be loaded in the ‘cycle-high’ register to get pulses of duty cycle 75%.
4 a. Given an analog input signal whose voltage ranges from 0 to 5 v and an 8-bit digital encoding, calculate the correct encoding for 3.5 v and then trace the successive approximation approach to find the correct encoding.
b. What is cache mapping? Explain the direct mapping techniques for cache. (08 Marks)
c. Explain the terms write ability and storage permanence.
5 a. Explain two level multibus architecture, with a neat diagram.
b. Compose lKx 8 ROMs into 2K x 16 ROM.
c. Given the following three cache designs, find the one with the best performance, by calculating the average cost of access. Show all calculations.
i) 4K byte, 8-way-set associative cache, with a 6% miss rate; cache hit costs one cycle, cache miss costs 12 cycles
ii) 8K byte, 4-way-set associative cache with a 4% miss rate; cache hit costs 2 cycles, cache miss costs 12 cycles
iii) 16K byte, 2-way-set associative cache with a 2% miss rate; cache hit costs 3cycles, cache miss costs 12 cycles.
6 a.What is interrupt latency? What are the factors affecting it?
b. Explain with an example, how the Round-Robin architecture works. When is it not suitable?
c. What is a reentrant function? Give the three rules to decide reentrant functions.
7 a. What is semaphore? Explain RTOS semaphore ’
b. Differentiate between hard and soft RTOS highlighting the advantages and disadvantages of each.
c. Explain‘deadly embrace’.
8 a. What is an event? Give three standard features of an event.
b. Give a comparison of methods for inter task communication.
c. Explain the two rules, that the interrupt routines must follow, in RTOS environment. What is the effect of blocking on interrupts? Explain with a diagram.
d. Explain the role of timer function in RTOS.