VTU Previous Question Papers BE CS 4th Semester Computer Organization Aug 2004

VTU Previous Question Papers BE CS 4th Semester

Computer Organization Aug 2004


Note: I. Answer FIVE Questions.

2. All questions carry equal marks.

1. (a) Consider the memory system of a computer storing the following data :

Address in Hex 2000 2001 2002 2003

Data stored (binary) 00111000  00110100 00110010  00111001


Interpret the storage as numbers in the manner indicated below and find their decimal values in each case.

i)    Big-en’dian storage of 2 hex words of 4 – digits each

ii)    Big-endian storage of 2 BCD words of 4 – digits each.

iii)   Little – endian storage, in ASCII, of a 4 – digit signed hex word.

iv)   Little endian storage, in ASCII, of a 4 – digit BCD word.

(b) Give reasons to justify using, generally’,

i)   Single address instructions in 8 – bit CPU’s

ii)   Double address instruction in 16-bit CPU’s

iii)  Three address instructions in RISC systems

In each of these systems give assembly language programs for performing the operation :

data at mem A + data at meb B –> memC.


2.  (a) What do you understand by stack frames ? Discuss their use in sub-routines.

(b) Write an assembly program to multiply 2 memory arrays and store their result in a third memory array :

a(i) * b(i) = c(i) for i — 0 to n — 1. Consider load/store and 3-address system.

3. (a) Explain how interrupt request from several I/O devices can be communicated to a processor through a single INTR line.

(b) Which- type of I/o devices are interfaced through DMA ? Explain the bus-arbitration process used for DMA.

4. (a) Explain the general features of interfacing a parallel I/o port to a processor.

(b) BO\3+- Consider the daisy chain arranement shown in fig Q.4b in which the bus request signal from the I/O is directly fed back as bus grant signal. Assume device IO/3 requests the bus and begins using it. When the device is finished, it deactivates BR3. Assume the delay from BGto BG in any device is d.

Show that a spurious bus-grant pulse will travel down stream from device 3. Estimate the width of this pulse.


5. (a) Describe SDRAM and DDR SD RAM operations for data transfer between main memory and cache memory systems.

(b) Consider a processor running a program 30% of the instructions of which require a memory read or write operation if the cache bit ratio is 0.95 for instructions and 0.9 for data. When a cache bit occurs for instruction or for data, only one clock is needed while the cache miss penalty is 17 clocks to read/write on the main memory. Work out the time saved by using the cache, given the total number of instructions executed is 1 million.


6. (a) Work out the multi level look – ahead carry scheme for doing a 32 bit number addition How many gate delays are required to do the complete addition in this method ?

(b) The hexa decimal value of 7r is 3.243 F6A8885 A308D3… Work out the IEEE standard representation (IEEE standard 754-1985) of 7 r in single and double precision formats.

7. (a) Show the basic organisation of a CPU in terms of registers and other units for a single bus data path CPU. In such a CPU, show the complete action of the CPU in fetching and executing the instruction.

Load i?! from memory data at A, where A is a memory address. Assume the instruction is in one process or word. Indicate the control signals to be used at each stage of execution.

 (b) Explain the basic concept of micro programmed control.

8. (a) With a block diagram explain the general requirements of a microwave oven OR a digital camera.

(b) Write short notes on any TWO.

i)   A good method of hardware multiplication

ii)  SCSI bus

iii) Virtual memory

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