VTU Previous Exam Papers BE EC 6th Semester Analog and Mixed Mode VLSI Design May/June 2010

VTU Previous Exam  Papers BE EC 6th Semester

 Analog and Mixed Mode VLSI Design May/June 2010

 

PART-A

1 a. Explain the characteristics and typical errors associated with sample and hold circuit.

b.   Briefly explain the ADC specifications.

c.   Find the resolution of DAC, if the output voltage is desired to change in 1 mV increments while using a reference voltage of 4V.

 

2 a. Explain qualitatively the architecture and working of charge scaling DACs.

b.  Design a 3-bit charge scaling DAC and find the value of output voltage for D2D1D0 – 100 and 011. Assume Vref = 5V, C = 0.5 PF.

c.   Briefly explain the architecture & working of a pipeline digital to analog coverter.

 

3  a. Explain the architecture and working of a flash ADC.

b.  If a 10-bit flash ADC is designed, determine maximum offset voltage .of comparators which will make INL less than lA LSB. Assume that resister string is perfectly matched and Vref -4 V.

c.   Briefly explain the block diagram of a 2-step flash ADC and its working.

 

4 a. Explain qualitatively preamplification and decision circuits of a CMOS

comparator unit. Draw their CMOS circuits,

b.  Explain the principle of an analog multiplier.

c.   Briefly explain CMOS analog multiplier with the help of a circuit diagram.

PART- B

5 a. Define SNR, effective number of bits and clock jitter in mixed signal circuits qualitatively.

b. Explain the principle of averaging to improve SNR, in mixed signal circuits.

c.   Briefly explain the role of decimating filters in ADCs.

 

6 a. With a neat process flow diagram, explain submicron CMOS technology and bring out the differences as compared to CMOS technology.

b.  Explain how capacitor and resister elements are fabricated in submicron technology.

c.   Explain MOSFET as a switch.

 

7 a. What are delay elements? Explain how they are realized using pass

transistors, inverters and C2MOS and TSPC circuits.

b.  Realize a 4-bit pipelined adder using latches and explain its operation.

c.   Implement lull adder using dynamic logic and explain.

 

8 a. Consider a small signal amplification of a floating current source shown in Fig.Q8(A). Assuming NMOS cascade o/p resistance is labeled Rncas, what is the small signal resistance scan by test voltage Vtest?

1

Fig.Q8(A)

b. Explain with the help of circuit diagrams, the technique of making the flow rate concern in the design of op amp.

 

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