VTU Previous Exam Papers BE EC 6th Semester Analog and Mixed Mode VLSI Design December 2010
VTU Previous Exam Papers BE EC 6th Semester
Analog and Mixed Mode VLSI Design December 2010
Note: Answer any FIVE full questions,
selecting at least TWO questions from each part
1 (a)With reference to a DAC describe :
i) Resolution ii) LSB iii) DNL iv) INL v) Vfs vi) Dynamic range.
Find the value of 1 LSB and VFs for a 4-bit, 8-bit and 10-bit DAC. VRef = 5V.
(b) Determine the DNL and INL for a 3-bit non-ideal DAC with the given output values. Comment on the monotonocity.
|Digital code||Analog value|
2 (a) Draw the transfer curve for a 3-bit ADC with ramp input. Explain what is quantization error. Plot the quantization error graph for an ideal ADC.
(b) Explain the mixed signal layout issues.
3 (a) Design a 3-bit DAC using binary switch array. Assume VRef = 5V and power dissipation 5mW. Find the analog value for the input D = 101. Draw the diagram and the path traced for D=101.
(b)With a neat diagram, explain the working of a cyclic DAC. Find the value of the output voltage at the end of each cycle for N = 4 VRef = 5 V and D = 1101.
4 (a)Explain the working of a successive approximation ADC, with a block diagram. For the ADC, give the intermediate values for VRef – 8V, N = 3 and Vjn = 3.5V.
(b)Explain the working of a voltage comparator, with the help of a block diagram.
5 (a) Give the Z domain representation of a two path averager and plot the magnitude and phase response of the digital filter.
(b)If the input sine wave to an averager has a peak amplitude of 0.5 V and a frequency of 20MHz, determine the peak amplitude of the
averager output and the delay through the circuit.
(c)Develop an expression for the effective number of bits, in terms of the measured SNR, if the input sinewave has a peak amplitude of
40% of VRef+ – VRef.
6(a) With the help of a block diagram, explain the accumulate and dump circuit.
Plot the general frequency response of an averaging filter.
(b)Specify the accuracy required of an 8-bit ADC, if it is to be used to attain 12 bits with INL and DNL of ± 0.5 LSBS Vaef- 1.5 V.
(c) Discuss the advantages and disadvantages of cascading averaging circuits to increase filter attenuation.
7(a) Explain the concept of interpolation.
(b) Explain how MOSFET behaves as a capacitor. Explain floating MOS capacitor.
(c) Explain the simple delay element using pass transistors and CMOS inverters.
8 (a) Draw the arrangement for a 4 -bit pipelined adder and full adder bit
implemented using dynamic logic.
(b)Explain the limitation of an inverter at the output of an op-amp, with the help of its transfer curve. How is it overcome?
(c) Explain true single phase clocking (TSPC). Using TSPC explain the delay element.