VTU Previous Exam Papers BE CS 4th Semester Computer Organization January 2010
VTU Previous Exam Papers BE CS 4th Semester
Computer Organization January 2010
1 a. With a neat diagram, explain in detail the functional units of a computer.
b. How the performance of a computer is measured? Assuming that the reference computer is Ultra SPARCIO workstation with 300MHz Ultra SPARC-III processor. A company has to purchase 500 new computers, hence ordered testing of a new computer with SPEC2000 (run on reference as well as new Computer). Following observations were made:
|Programs||Runtime on reference computer||Runtime in new computer|
|1||50 Minutes||5 Minutes|
|2||75 Minutes||4 Minutes|
|3||60 Minutes||6 Minutes|
|4||30 Minutes||3 Minutes|
The company’s system manager will place the orders for purchasing new computers only if the overall SPEC rating is at least 12.00. After the said test, will the system manager place order for the purchase of new computers?
2 a. Convert the following pairs of decimal numbers to 5 bit signed 2’s complement binary numbers and add them. Also state whether overflow occurs in each case, i) -5 & 7 ii) -3 & -8 iii) -10 & -13.
b. Write a program which evaluates the expression AxB+CxD in a single accumulator processor. Assume that processor has load, store, multiply and add instructions and all the values fit in the accumulator.
c. Explain how the parameters are passed to a subroutine? Write a program to multiply a list of ‘n’ numbers stored in memory, which calls a subroutine namely, LISTMUL and trace the program with suitable example.
3 a. In modem computers, why interrupts are required? Support your claim with a suitable example.
b. In the interrupt mechanism, how the simultaneous arrivals of interrupts from various (multiple) devices (I/O) are handled?
c. With neat sketches, explain the various approaches to bus arbitration.
4 a. With a neat sketch, explain the individual input and output interface circuits. Also elicit their salient features.
b. In a computer system, why a PCI Bus is used? With a neat sketch, explain how the read operation is performed, along with the role of IRDY# / TRDY#, on the PCI Bus.
5. a. Draw a diagram and explain the working of a 16 mega bit DRAM chip configured as 2Mx8. Also explain as to how it can be made to work in fast page mode.
b. Assume that a computer has LI and L2 caches. The cache blocks consist of 8 words. Assume that the hit rate is same for both caches and that it is equal to 0.95 for instructions and 0.90 for data. Assume also that the times needed to access an 8-word block in these caches are Cj^l cycle and C2 = 10 cycles, then answer the following:
i) What is the average access time experienced by the processor if the main memory uses interleaving where the memory access parameters have usual meaning (M= 17 with interleaving & M-38 without interleaving, assume that 30% of the instructions in a typical program perform a read or write operations).
ii) What is the average access time if the main memory is not interleaved?
iii) What is the improvement obtained through interleaving?
6 a. Explain in detail, the working principle of a magnetic hard disk.
b. A disk unit has 24 recording surfaces. It has a total of 14,000 cylinders. There are an average of 400 sectors per track. Each sector contains 512 bytes of data. Answer the following questions.
i) What is the maximum no. of gigabytes that can be stores in this unit?
ii) What is the data transfer rate in bytes/sec at a rotational speed of 7200 rpm?
iii) Using a 32-bit word, suggest a suitable scheme for specifying the disk address, assuming that there are 512 bytes/sector.
7 a. Draw circuit diagram for binary division. Explain the restoring and non-restoring division algorithms with suitable examples.
b. Explain the concept of carry save addition for the multiplication operation, MxQ-P for 4-bit operands, with diagram & suitable example.
8 a. Explain the process of fetching a word from memory using timing diagram of memory read operation. Also give an example for the same.
b. Write the control sequence of execution of the instruction ADD (R3VR1. For this sequence of instructions the processor is driven by a continuously running clock such that each control step is 2 ns in duration. How long will the processor have to wait in steps 2 & 5, assuming that a memory read operation takes 16 ns to complete? Also compute the percentage of time for which the processor is idle during the execution of this instruction.