VTU Previous Exam Papers BE CS 4th Semester Computer Organization January 2009

VTU CSE 4th Semester Computer Organization January 2009

VTU CSE 4th Semester Computer Organization Question Paper January 2009: Exam papers will give you an idea about the actual exam. By practicing more papers you will easily identify the important topics from every chapter. That will help you to score better marks. It will give you information about the important chapters and concepts to be covered in all chapters.

Here we are providing you the complete guide on VTU CSE 4th Semester Computer Organization Question Paper January 2009.

VTU CSE 4th Semester Computer Organization Question Paper January 2009

You must have Computer Organization Question Paper along with the latest Computer Science 4th sem Syllabus to enhance your semester exam preparation.

Here you can check the VTU CSE 4th Semester Computer Organization Question Paper January 2009

Note : Answer FIVE full questions, selecting at least two questions from each Part A and Part B.

Part A

1 a. Explain the different functional units of a computer with a neat block diagram.

b.  Write the basic performance equation. Explain the role of each of the parameters in the equation on the performance of the computer.

c.   Represent the number 81234561 in 32-bit Big-endian and little-endian memory organization.

2  a. What is the need for an addressing mode? Explain the following addressing modes with examples: immediate, direct, indirect, index, relative.

b.  What is subroutine linkage? How are parameters passed to subroutines?

c.   What is a stack frame? Explain.

3 a. Discuss the different schemes available to disable and enable interrupts.

b.  How are simultaneous interrupt from more than one devices handled?

c.   What does the term “cycle stealing” mean?

d.  Write a note on any one bus arbitration scheme.

4 a. Draw and explain the block diagram of a typical serial interface. How does it compare with a parallel interface?

b. Explain the main phases involved in SCSI bus operation.

 Part B

5 a. Differentiate between SRAM and DRAM.

b.  Sketch and explain the internal organization of a 2M x 8 dynamic memory chip.

c.   Explain any one cache mapping function.

d. A computer has byte addressable memory with a cache that can hold eight 32-bit words. Each cache block consists of one 32-bit word. The following sequence of hex addresses is read during program execution: 200, 204, 208, 20C, 2F4, 2FO, 200, 204, 218, 21C, 24C, 2F4 Assuming that the cache is initially empty, show the contents of the cache if i) direct mapping is used ii) associative mapping with LRU replacement is used.

6 a. Draw a block diagram and explain how a virtual address from the processor is translated into a physical address in the main memory.

b.  Write notes on: i) Optical technology used in CD systems ii) RAID Disk arrays.

c.   Draw a figure to illustrate and explain a 16-bit carry look ahead adder using 4-bit adder blocks. Show that the carry and sum are generated in 5 and 8 gate delays respectively.

7 a. Draw the hardware implementation of Booth’s multiplication algorithm.

b. Trace the steps in the above implementation to multiply -5 x -4.

c.   Illustrate the steps for non-restoring division algorithm on the following data: dividend ~ 1011, divisor = 0101.

d.  If A and B are two single precision floating point numbers where A – 44900000H and B – 42A00000H Show the results of (A+B) and (A-B).

8 a. Draw a figure of the single bus organization of the processor unit.

b.  List the actions needed to execute the instruction Add Rl, (R3). Write the sequence of control steps to perform the actions for a single bus structure. Explain the steps. (10 Marks)

c.   Compare hard wired control unit with micro programmed control unit.

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