# VTU Previous Exam Papers BE CS 3rd Semester Logic Design May/June 2010

To score the better mark in the Logic Design semester exam, you must solve the previous exam Paper. It will give you information about the important chapters and concepts to be covered in all chapters.

Here we are providing you the complete guide on VTU CSE 3rd Semester Logic Design Question Paper June 2010.

## VTU CSE 3rd Semester Logic Design Question Paper June 2010

You must have Logic Design Question Paper along with the latest Computer Science 3rd sem Syllabus to enhance your semester exam preparation.

Here you can check the VTU CSE 3rd Semester Logic Design Question Paper June 2010

Note: Answer any FIVE full questions, selecting at least TWO questions from each part

PART-A

1 a. Simplify the given Boolean function by using K-map method and express it in SOP form. Realise logic circuit by using NAND gates only. f(A,B,C, D) = (m(7, 9, 10, 11, 12, 13, 14, 15))

b.  Simplify following Boolean function by using K-map method in POS form: f (A, B, C, D) = m(0,1,2,3,4,5,7)

c.   Find prime implicants for the Boolean expression by using Quine McClusky method, f (A, B, C, D) = ]T (1,3,6,7,8,9,10,12,14,15) + d(l 1,13)

2 a. Define decoder. Draw logic diagram of 3:8 decoder with enable input.

b. Implement the given Boolean function by using 8:1 multiplexer. f(A,B,C,D) = ]T(0,l, 3,5,7,11,12,13,14)

c. With a neat diagram, explain the decimal to BCD encoder.

3 a.What are the three different models for writing a module body in verilog HDL? Give example for any one model.

b.   With truth table and a neat logic diagram, explain full adder implementation.

c.   Explain how IG 7483 can be used as 4 bit adder/subtractor.

4 a. With transfer characteristic, explain how Schmitt trigger converts a random waveform into a rectangular waveform.

b.  Explain basic S.R flip-flop by using NOR gate. What is the drawback of S~R flip-flop? How J-K flip-flop is obtained from S-R flip-flop?

c. Find out characteristic equations of J-K flip-flop and D flip-flop.

PART-B

5 a. Explain any two types of shift register with waveforms. How Johnson counter is obtained from shift register?

b.  Design Mod-6 synchronous counter by using J-K flip-flop. Give excitation table of J-K flip-flop, state diagram and state transition table.

6 a. Differentiate between Moore and Mealy model of synchronous sequential circuit.

b. Reduce the state transition diagram of Mealy model by row elimination method and implication table method. State transition diagram. r

Fig. Q6 (b)

7 a. Explain with neat diagram, R-2R ladder type 4 bit D to A converter. Find out analog output if input is 1100 and T- +5 volts. For 10 bit DAC if full scale output is 10.24 volts, what is resolution?       (10 Marks)

b. Explain with a neat diagram, successive approximation type DAC.

8 a. With a neat circuit diagram, explain the operation of a two input TTL NAND gate with tolem pole output.

b.  Explain with a neat diagram, CMOS inverter.

c.   Explain CMOS characteristics.

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