VTU Old Exam Papers BE EC 4th Semester
Fundamentals of HDL June 2010
Note: Answer any FIVE full questions, selecting at least TWO questions from each part.
1 a. Explain the behavioral and structural description types of HDL programming, with examples and keywords used.
b. Explain the following data types:
i) Physical std_logic and bit_vector in VHDL
ii) Nets* parameters and registers in verilog.
2 a. How do you assign a delay time to the signal assignment statement? Explain the dataflow model of 2x 1 multiplexer in VHDL and verilog.
b. Explain the use of data type vectors with dataflow description of 2×2 unsigned combinational array multiplier in VHDL and verilog.
3 a. Differentiate between signal and variable assignment statement in VHDL. Write VHDL programs for behavioral description of D-iatch using signal assignment and variable assignment.
b. Explain the formats of for-loop and while-loop statements in VHDL and verilog. C. Write verilog description for a 4-bit priority encoder.
4 a. Explain the binding in the following, with example:
i) Between entity and component in VHDL
ii) Between two modules in verilog.
b. Write the HDL programs for N+l bit magnitude comparator using i) generate and generic in VHDL ii) generate and parameter in verilog.
5 a. Explain the use of procedure (in VHDL) and task (in verilog) with description of full adder, using half adders.
b. Explain the file declaration and built in procedures for file handling in VHDL.
6 a. How to attach a package to the VHDL module? Explain with an example.
b. What, is the need of mixed type descriptions? Write description of 16×8 SRAM in VHDL and verilog.
7 a. How to imvoke a VHDL entity from a verilog module. Explain with an example.
b. Write a HDL program for mixed language descriptions of a JK-flip-flop with a clear input.
8 a. Write a flow diagram of synthesis. Explain its steps.
b. Write VHDL code for signal assignment statement y – 2 x + 3. Show the synthesized logic symbol and gate level diagram. Write structural code in virology using the gate level diagram.