VLSI Testing Syllabus NIT Jalandhar
EC-467 VLSI Testing [3 0 0 3]
Introduction -Scope of testing and verification in VLSI design process. Problem in analog and digital testing. Logic simulation & Fault modelling: Circuit Modelling Compiled simulation Event-driven simulation. Simulation Techniques. Fault detection and redundancy. Fault equivalence and fault dominance. Stuck-at faults bridging faults, transistor faults, delay faults etc. Fault Detection using Boolean Difference. Path Sensitization Fault Collapsing.
Testing Algorithm for Combinational Circuits: Introduction to combinational circuit, Problems in
combinational circuit testing,D- Algorithm, Boolean Difference, Podem; Random, Deterministic and Weighted Random Test Pattern Generation; ATPG Testing Generation for Sequential Circuit: . Models of Sequential Circuits, State Table Method, Self Initializing Test Sequences, Undetectability, Distinguishing and Synchronizing Sequences. Complexity Sequential ATPG
PLA Testing: Cross Point Fault Model and Test Generation, PAL Testing
Memory Testing: Different method of memory testing, Marching Tests; Delay Faults; BIST BIST for testing of logic and memories
Recent Trends in VLSI Testing
1. M. Bushnell and V. D. Agrawal, “Essentials of Electronic Testing for Digital, Memory and
Mixed- Signal VLSI Circuits”, Kluwer Academic Publishers, 2000.
2. M. Abramovici, M. A. Breuer and A. D. Friedman, “Digital Systems Testing and Testable
Design”, IEEE Press, 1990.
3. T.Kropf, “Introduction to Formal Hardware Verification”, Springer Verlag, 2000.
4. P. Rashinkar, Paterson and L. Singh, “System-on-a-Chip Verification-Methodology and
Techniques”, Kluwer Academic Publishers, 2001.
5. J.M. Rabaey, A. Chandrakasan and B. Nikolic: Digital Integrated Circuits- A Design Perspective,
2nd ed., PHI, 2003