# Digital Logic Theory and Design BE Third Sem

Title of the Paper :Digital Logic Theory and Design Max. Marks :80
Sub. Code :6C0065 Time : 3 Hours
Date :22/04/2010 Session :AN
PART – A (10 x 2 = 20)
1. Given the two binary numbers X = 1010100 and Y = 1000011,
perform the subtraction (a) X – Y and (b) Y – X using 2’s
complements.
2. State De Morgan’s theorem.
3. Compare CMOS and NMOS.
4. What are tri-state gates?
5. Give the comparison between combinational circuits and
sequential circuits.
6. Difference between PROM, PLA, PAL.
7. What is race around condition?
8. Explain the procedure for state minimization.
9. Define race.
10. What are essential hazards?
PART – B (5 x 12 = 60)

(or)
12. (a) Perform l’s complement and 2’s complement addition for +45
and -35.
(b) Simplify the expression
Y = S m (1, 4, 5, 7, 8, 9, 11) using Karnaugh map.
13. Draw and explain the circuit diagram of a basic totem-pole TTL
NAND gate. Discuss about its characteristics and specification.
(or)
14. Draw and explain the circuit diagram of CMOS Inverter gate.
Discuss about its characteristics and specification.
15. (a) Design a 3-to-8 decoder.
(b) Implement F(A, B, C, D) = S (0,1,2,5,7,11,15) using 8-to-1
multiplexer.
(or)
16. (a) Design a 4-bit binary-to-gray-code converter.
(b) Design a full subtractor.
17. (a) Explain JK – FF with logic diagram, characteristic table and
equation, present state-next state table, state diagram and
application/excitation table.
(b) Explain the realization of JK – FF from SR – FF.
(or)
18. Design and hence explain the working of a 4-bit ripple counter.
19. Design an synchronous sequential circuit with two inputs X and
Y and with one output Z. Whenever Y is 1, input X is transferred
to Z. When Y is 0, the output does not change for any change in
X. Use JK FF for implementation of the circuit.
(or)
20. What are the hazards that occur in asynchronous sequential
circuit? What are the ways in which they can be eliminated?