RTU Previous Year Question Papers BE CSE 5th Semester
Computer architecture Dec 2011
1 (a) Explain the following terms with reference to non Von- Neumann machines.
(b) A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers.
(i) How many selection input are there in each multiplexers?
(ii) What size of multiplexer are needed?
(iii) How many multiplexer are there in the bus ?
(a) Draw the block diagram for the hardware that implements
t + pq : A «- A+B where A and B are two n-bit resisters and t, p and q are control variables show the logic gate for the control function.
(b) Design a N-bit combinational circuit decrementer using four full-adder circuits.
2. Write a program to evaluate the arithmetic statement :
(i) Using a general register computer with three address instruction.
(ii) Using a general register computer with two address instruction.
(iii) Using an accumulator type computer with one address instructions
(iv) Using a stack organized computer with zero-address operation instructions.
2. (a) The memory unit of a computer has 256 K words of 32 bit each. The computer has an instruction format with four field : an operation code field, a mode field to specity one of seven addressing modes, a register address field to specify one of 60 processor registers and a memory address. Specify the instruction format and the number of bit in each field if the instruction is in one memory word.
(b) A computer has 32-bit instruction and 12-bit addresses. If there are 250 two address instruction, how many one address instruction can be formulated ?
3 (a) Derive an algorithm in flowchart term for adding and subtracting two fixed-point binary numbers when negative numbers are in signed-is compliment representation.
(b) Design an array multiplier that multiplies two 4-bit number. Use AND gates and binary address.
3 (a) Show that when we multiply two n-digit number in base no overflow occurs. The multiplication gives a product of 2nd digits in length.
(b) Derive an algorithm in flow chart form for the non restoring method of fixed-point binary division.
UNIT – IV
4. (a) Construct a memory system having static 1Kx4 RAM. How
many such RAM’s will be required to
(i) construct 1Kx8 RAM bank ?
(ii) 4E x 4 RAM memory bank ? Show the block diagram and the address decoding circuit.
(b) Write short note on : Virtual memory.
(a) An address space is specified by 24 bits and the corresponding memory space by 16 bits.
(i) How many words are there in the address space ?
(ii) How many words are there in the memory space ?
(iii) If a page consists of 2K words, how many pages and block are there in the system ?
(b) In a two level virtual memory, tA1 = 10‘7 S and tA2 = 10′2 S. What must be the hit ratio H be in order for the access efficiency to be at least 90% of its maximum possible value ?
5. (a) Design a parallel priority interrupt hardware for a system with eight interval sources.
(b) Why does DMA have priority over the CPU when both request a memory transfer ?
(a) List the advantage and disadvantage with respect to program design complexity, 10 bandwidth, and interface hardware costs for the following 10 control methods.
(i) programmed 10
(b) Why are the read and write control line in a DMA controller bidirectional ? Under what condition and for what purpose are they used as inputs ? Under what condition and for what purpose are they used as outputs ?